401 Physical Verification Jobs - Page 6

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Additional General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 5+ years Hardware Engineering experience or related work experience. 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 5+ years Hardware Engineering experience or related work experience. 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm Hexagon DSP IP's 8+ years of experience in Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Work closely with CAD and custom macro/memory design leads to understand the design methodology and high level requirements and develop flows. Develop efficient analysis and model generation methodologies for timing and noise to achieve tight correlation. Determine key areas where automation and leading methodologies can help improve PPA. Define, innovate and implement new infrastructure capabilities that can be used to accelerate design and development, and improve user experience. Preferred qualifications MS degree in Computer Engineering; 5+ years of practical experience Strong skills in transistor level signoff tools for timing, emir, simulations, extraction and IPQA. Experience in flow development at high scale (multithreading, ml capabilities, hyperscaling, schedulers, filer hot-spot management etc.). Direct experience with efficient visualization tools to analyze results, log parsers, web views, error/warning scanners etc. Strong fundamentals in scripting languages (python, tcl, sh. others), automation, general purpose CAD infrastructure and flows. Good understanding of stdcell or memory design fundamentals. Excellent partner collaborating with design team in flow debug and support. Experience with signing off accuracy and correlation of analysis flows (compare to spice, foundry models, etc.) Tool knowledge in any of these is a plus – nanotime, xa/spectre, liberate, primelib, totem

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Overview Experienced STA/Timing Engineer with 3-10 Years of hands-on experience on timing sign off/convergence for complex SOCs. Ability to start immediately on timing analysis/sign-off with PD/Methodology teams across multiple sites and different technology nodes. : STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills. Willing to work in cross-collaborative environment. Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo. Education B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling. Hands-on experience with STA tools - Prime-time, Tempus Have experience working on timing convergence at Chip-level and Hard-Macro level. In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows, methods, and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages – TCL, Perl, Python Basic knowledge of device physics

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Design Planning. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Verification. Experience1-3 Years.

HW Physical Design macros with Innovus and ICC2 tools. block implementation such as floorplanning, placement, clock tree synthesis, routing and optimization. signoff closure related fixes and runs ,formal verification and physical verification.

Sr.Executive/Executive - Fixed Assets - Dodla Dairy Sr.Executive/Executive Fixed Assets Role & responsibilities Creation and Capitalization of Assets: Responsible for the proper creation and capitalization of fixed assets in the system as per company policies and accounting standards. Coordination for Asset Transfers and Disposal: Work closely with various departments to gather asset transfer and disposal information, ensuring all data is accurately posted in the system. Verification of Original Asset Invoices: Verify original invoices for assets and ensure they are recorded correctly in the fixed asset register. Preparation of Reports: Prepare key reports such as CWIP aging report, fixed asset schedules, CAPEX cash outflow report, CWIP movement, and the Schedule III format in compliance with regulatory requirements. Auditor Coordination: Provide required information and schedules to internal and external auditors for audits related to fixed assets. Physical Verification of Assets: Assist in the preparation of asset lists for tagging and support the physical verification of fixed assets. Project Accounting: Handle project accounting for capital projects, ensuring accurate cost allocation and timely capitalization of assets. Depreciation Calculation: Perform monthly depreciation calculations for fixed assets in line with company policies and accounting standards. Apply for this position Allowed Type(s): .pdf, .doc, .docx By using this form you agree with the storage and handling of your data by this website. *

Sr DFT Engineers and Managers - location remote any where in India Job Summary Our clients Arasan Chip Systems (www.arasan.com) based in US are seeking for their India Development Center Senior and Experienced DFT Engineer with 68 years of hands-on expertise in Design-for-Test methodologies and implementation for complex SoC designs. The candidate will be responsible for developing and integrating DFT architectures, driving ATPG and MBIST flows, and working closely with RTL design, physical design, and test teams to ensure high test coverage and silicon readiness. Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Generate and validate test patterns (stuck-at, transition, path delay). Collaborate with RTL, synthesis, and physical design teams to ensure DFT integration and timing closure. Participate in silicon bring-up and ATE support. Support internal reviews, audits, and DFT documentation. Skills Strong experience with industry-standard DFT tools (Mentor Tessent, Synopsys DFTMAX, Cadence Modus, etc.). Hands-on experience in scan insertion, ATPG, MBIST, boundary scan, and test compression techniques. Familiarity with ATE pattern generation and silicon debug flows. Solid understanding of RTL/gate-level simulation, synthesis, STA, and timing-aware DFT flows. Proficiency in scripting languages (TCL, Perl, Python) for automation. Excellent analytical and problem-solving skills. Qualifications B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field. 6–8 years of relevant experience in DFT for ASIC/SoC design. Preferred Exposure to low-power DFT methodologies (UPF/CPF flows). Prior experience with automotive or high-speed PHY IP integration is a plus. Knowledge of IEEE standards (1149.1, 1500, 1687).

90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

MTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 4+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Bangalore / Hyderbad #LI-PK2

At Mott MacDonald, we are proud to be part of an ever-changing global industry, delivering transformative work that s defining our future. It s our people who power that performance. We re a collection of leading experts who combine our different expertise to stay ahead of the curve and move the industry forward. With so many opportunities to learn, grow and excel, the possibilities are as varied as every individual to shape the career that s right for you. Whether you want to pursue excellence in a specialism or broaden your experience with flexible roles across our business, you re connected to a community of global experts championing you to be your best. Key Responsibilities: Supports Manager with treasury operations including Prompt processing of payments and accounting of payment and receipt transactions Liaising with bank and business team and obtaining bonds from bank effectively Efficient cash management and placing of fixed deposits with bank Submission of accurate and timely monthly/annual reports to bank Accurate and timely preparation of monthly cashflow and annual cashflow budget Assist in the maintenance of fixed asset register, prompt recording of movement, sale and discard of the asset, carrying out periodical physical verification and perform reconciliation. Ensure posting of depreciation journal as per statutory requirements Assist during Statutory and Internal Audits as required Accurate and timely preparation of Inter-co reconciliation, Balance sheet reconciliation, etc. Any other tasks that may be assigned from time to time Essential Candidate Requirements: Education Qualification - M com / MBA (full time) from reputed institute Experience in the field of treasury would be an added advantage Strong analytical ability with effective communication and interpersonal skills Conversant in the use of Microsoft products and experience in other ERP systems Proven ability to produce accurate reports for compliances to tight deadlines Flexible to work with changing environment As a proudly employee-owned business, we re here to benefit our clients, our communities and each other. Our shared success enables us to invest in creating a platform for everyone to feel safe and valued, empowered with the right tools and right support, in a place where fairness and integrity run deep. Whatever your ambition, Mott MacDonald is where everyone has the opportunity to be brilliant. We can offer (subject to Company s policy): - Agile and safe working environment - Competitive annual leave and sick leaves - Group incentive scheme - Group term life insurance, Workmen s compensation and Group medical insurance coverage - Short and Long-term Global employment opportunities - Global collaboration and knowledge sharing - Digital Innovation and Transformation

In your new role you will: Responsible for leading Physical Design and Timing Closure of low-power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design,methodology and process aspects. Enable next generation of place and route engineers via mentoring and thought leadership. You are best equipped for this task if you have: Hands-on experience in physical design implementation and timing closure of large blocks/top Expert user of industry standard tools for physical design and signoff. Expert in scripting languages (shell, perl, TCL) and Make flow In-depth knowledge of DSM technologies and associated physical design challenges Deep understanding of low power design techniques and implementation methodologies Should be self-motivated and take initiatives to drive new methodologies Should have strong written and verbal communication skills We are on a journey to create the best Infineon for everyone.

Main Tasks (1) Physical verification of Gold Packets, Cash including Vault Cash and Foreign Currency as to its correctness with the system records. (2) Checking of ornaments as to its quantity, weight, quality and purity taken for pledge during the current gold inspection period. (3) Checking of greater than 5 months gold packets as to its quantity, weight, quality and purity for which gold inspections were done earlier. (4) Verification of Gold Loan pledge/release documents and reporting of anomalies if any observed. (5) Verifying whether the ornaments pledged under all schemes are solid ornaments and LP/SP ornaments are not accepted for pledge under any schemes. (6) Verification and reporting of any overdue gold loans, Low Purity and Spurious accounts are re-pledged or re-pledged under higher rate. (7) Verification of Documents and ornaments/coins for Swarnavarsham/Shwethavarsham Loans disbursed. (8) Verification of all Gold Loan related products/Packets, MSME Packets, Mahilamitra Loan Packets and Chitty Security Packets etc. (9) Conducting Handing over/Taking over of branch as and when required by the Management and sending reports of the same to BAI Dept. (10) Purity Index updation in the system (11) Verification and sealing of auction related packets. (12) Participating in the Gold Auction conducted in various branches as per the instruction from the Department Head (13) Conducting Special Inspection in Selected branches along with Internal Auditors as per instruction from HO Audit. (14) Verification of Bulk Pledge Packets, Balance Transfer Pledges, Doubtful Pledges as per the instruction from HOD. (15) Conducting Gurukul Training and Appraisal training to be given to Branch staff during Gold Inspection. (16) Other Key activities instructed by the Management on Demand. Areas Of Responsibility (1) Timely Reporting of discrepancies observed from the new & old packets Verification. (2) Reporting of observations/anomalies which are not rectified by the branch from the earlier inspections. (3) Immediate reporting of spurious ornaments found during the current Gold Inspection. (4) Verifying the each and every release of Gold Ornaments made during the period of inspection as the GI act as Joint Custodian during the period of audit. (5) Sending various reports as required by the BAI Dept. (6) Observing and reporting confidentially any malpractices made by the branch staff. (7) Reporting of acceptance for pledge certain type of ornaments like Cumbum chain, Karimani chain etc instructed not to be accepted for pledge by Management. (8) Verification of Gold Ornaments pledged by Pawn Brokers and give instruction to Branches to strictly avoid it & verification of Gold Packets relating to registered letters returned. Special Requirements - Compensation Band Based on Market Standards/Internal norms Entitlements As per policy Stake Holders MFL Staff, Group Company Staff Assets Required As per policy Career Progression As per policy Educational Qualification Minimum Graduation with 2-3 yrs of Gold Appraisal experience Preferred. Willing to Travel. Technical Qualification Basic Computer Knowledge, esp.MS Office applications mandatory Skills - Communication Skill Conversant in local language & English (proficiency in read, write and speak required)

Physical verification of Cash in hand, Foreign currency, and Gold packets as to its correctness with the Computer records. Checking of ornaments as to its quantity, weight, quality, and purity taken for pledge during the current gold inspection period. Random checking of gold packets as to its quantity, weight, quality, and purity for which gold inspections were done earlier. Verification of Gold Loan pledge/release documents and reporting of anomalies if any observed. Checking and reporting whether any overdue gold loans are re pledged under higher rate Verifying whether all the ornaments pledged under discharge scheme are solid ornaments, low purity and stoned ornaments are not accepted for pledge under discharge scheme Conducting handing over/Taking over of branch as and when required by the Management and sending reports of the same to HO. Reporting any discrepancies observed about the new & old packets checked Reporting of any observations/anomalies not rectified by the branch Immediate reporting of spurious ornaments found during the current Gold Inspection Sending various reports as required by the RM Dept. Verification of Gold Ornaments pledged by Pawn Brokers and given instruction to Branches strictly avoid it & verification of Gold Packets relating to registered letters returned.

Physical verification of Cash in hand, Foreign currency, and Gold packets as to its correctness with the Computer records. Checking of ornaments as to its quantity, weight, quality, and purity taken for pledge during the current gold inspection period. Random checking of gold packets as to its quantity, weight, quality, and purity for which gold inspections were done earlier. Verification of Gold Loan pledge/release documents and reporting of anomalies if any observed. Checking and reporting whether any overdue gold loans are re pledged under higher rate Verifying whether all the ornaments pledged under discharge scheme are solid ornaments, low purity and stoned ornaments are not accepted for pledge under discharge scheme Conducting handing over/Taking over of branch as and when required by the Management and sending reports of the same to HO. Reporting any discrepancies observed about the new & old packets checked Reporting of any observations/anomalies not rectified by the branch Immediate reporting of spurious ornaments found during the current Gold Inspection Sending various reports as required by the RM Dept. Verification of Gold Ornaments pledged by Pawn Brokers and given instruction to Branches strictly avoid it & verification of Gold Packets relating to registered letters returned.

Main Tasks (1) Physical verification of Gold Packets, Cash including Vault Cash and Foreign Currency as to its correctness with the system records. (2) Checking of ornaments as to its quantity, weight, quality and purity taken for pledge during the current gold inspection period. (3) Checking of greater than 5 months gold packets as to its quantity, weight, quality and purity for which gold inspections were done earlier. (4) Verification of Gold Loan pledge/release documents and reporting of anomalies if any observed. (5) Verifying whether the ornaments pledged under all schemes are solid ornaments and LP/SP ornaments are not accepted for pledge under any schemes. (6) Verification and reporting of any overdue gold loans, Low Purity and Spurious accounts are re-pledged or re-pledged under higher rate. (7) Verification of Documents and ornaments/coins for Swarnavarsham/Shwethavarsham Loans disbursed. (8) Verification of all Gold Loan related products/Packets, MSME Packets, Mahilamitra Loan Packets and Chitty Security Packets etc. (9) Conducting Handing over/Taking over of branch as and when required by the Management and sending reports of the same to BAI Dept. (10) Purity Index updation in the system (11) Verification and sealing of auction related packets. (12) Participating in the Gold Auction conducted in various branches as per the instruction from the Department Head (13) Conducting Special Inspection in Selected branches along with Internal Auditors as per instruction from HO Audit. (14) Verification of Bulk Pledge Packets, Balance Transfer Pledges, Doubtful Pledges as per the instruction from HOD. (15) Conducting Gurukul Training and Appraisal training to be given to Branch staff during Gold Inspection. (16) Other Key activities instructed by the Management on Demand. Areas Of Responsibility (1) Timely Reporting of discrepancies observed from the new & old packets Verification. (2) Reporting of observations/anomalies which are not rectified by the branch from the earlier inspections. (3) Immediate reporting of spurious ornaments found during the current Gold Inspection. (4) Verifying the each and every release of Gold Ornaments made during the period of inspection as the GI act as Joint Custodian during the period of audit. (5) Sending various reports as required by the BAI Dept. (6) Observing and reporting confidentially any malpractices made by the branch staff. (7) Reporting of acceptance for pledge certain type of ornaments like Cumbum chain, Karimani chain etc instructed not to be accepted for pledge by Management. (8) Verification of Gold Ornaments pledged by Pawn Brokers and give instruction to Branches to strictly avoid it & verification of Gold Packets relating to registered letters returned. Special Requirements - Compensation Band Based on Market Standards/Internal norms Entitlements As per policy Stake Holders MFL Staff, Group Company Staff Assets Required As per policy Career Progression As per policy Educational Qualification Minimum Graduation with 2-3 yrs of Gold Appraisal experience Preferred. Willing to Travel. Technical Qualification Basic Computer Knowledge, esp.MS Office applications mandatory Skills - Communication Skill Conversant in local language & English (proficiency in read, write and speak required)

Job Overview: Cadence Design Systems is looking for a highly motivated software engineer to work with the R&D engineering team in the Digital & Signoff Group. R&D Software Engineering role in Physical Verification area is a multi-faceted position encapsulating a mix of physical verification software development, algorithm development, software debugging, performance optimization, accuracy analysis, GUI development and integration with layout/schematic editors. R&D engineers collaborate with a large team of EDA professionals across multiple geographical regions to create and deliver best in class next generation software for physical IC application. R&D engineers work on complicated applications and interface them with other applications in a large suite of highly connected modules to enable next-generation physical verification solutions with superior performance and usability. R&D engineers develop code that satisfies the requirements for successful semiconductor design deployment. As R&D Engineer you will be part of a team responsible for designing, developing, troubleshooting, debugging and supporting critical projects. You will have a chance to contribute to the main Physical Verification flows in EDA industry and your work will be visible through billions of electronic devices deployed worldwide. Job Responsibilities: As Lead Software Engineer, this person will be responsible for the following software engineering activities: Write code implementing product requirement specifications Write and maintain unit tests and other tests as needed for implemented features and enhancements Participate in code reviews. Work with PE (Product Engineering) and QPV (Quality Product Validation) to review code quality and coverage of requested functionality Provide code fixes as requested by bug tracking system This person should have personality & communication skills for working within the R&D group, and with cross functional groups, such as PE, QPV, CM This person should be able to work independently, being able to collaborate remotely with team members. Job Qualifications: 5+ years of C++ development using object-oriented methodology Understand algorithm complexity and data structures Be able to write and debug multithreaded applications Have good experience writing Qt-based applications (model-view is mandatory) Successful candidate should have the knowledge of LISP or Tcl. Educational Qualification: BE/BTech/ME/MTech in CS/ECE/EE or equivalent Additional Skills/Preferences: experience with physical verification schematic and layout design experience with SKILL programming object oriented design basics Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Key Responsibilities: Floor planning: Develop and optimize floorplans for ASIC designs, ensuring optimal placement of cores, macros, and I/O cells while considering performance and manufacturability. Place & Route (P&R): Perform place-and-route tasks, optimizing for timing, power, and area, ensuring congestion-free routing and maximizing PPA (Performance, Power, Area). Static Timing Analysis (STA): Carry out static timing analysis to identify violations and work on techniques for timing closure such as resizing, retiming, or re-optimization. Power Analysis & Optimization: Perform power analysis, targeting low-power designs using techniques such as clock gating, power gating, and low-power state optimization. Signal Integrity & Noise Analysis: Perform signal integrity analysis to avoid noise and crosstalk in the design. Design Rule Check (DRC) and Layout vs. Schematic (LVS): Run DRC and LVS checks to ensure the layout adheres to manufacturing rules and matches the schematic. RC Extraction: Perform parasitic extraction and analyze RC effects to ensure the design functions at the required operating frequencies. Verification: Participate in the final sign-off processes for physical design and support tape-out efforts, ensuring all design specifications are met. Collaboration: Work closely with design, verification, and CAD teams to troubleshoot and resolve any design-related issues. Documentation: Maintain clear documentation throughout the physical design flow for ease of understanding and for future reference. Qualifications: Education: Bachelors/Masters degree in Electronics/Electrical Engineering or a relevant degree. Experience: Minimum 3-14 years of experience in ASIC physical design. Proficiency in place and route (P&R), static timing analysis (STA), power analysis , and DRC/LVS checks. Experience with tools like Cadence Innovus , Synopsys IC Compiler , or Mentor Graphics for physical design. Knowledge of advanced process nodes (e.g., 7nm, 5nm) is a plus. Technical Skills: Proficiency in digital design concepts and semiconductor process flows. Strong knowledge of timing optimization techniques and power optimization strategies. Familiarity with parasitic extraction and signal integrity analysis. Ability to script in languages like Tcl , Python , or Perl to automate tasks. Preferred Skills: Experience with 3D IC design or FinFET technologies. Familiarity with full-chip tape-out procedures. Exposure to machine learning techniques in physical design optimization will be added advantage.

SE NIOR SILICON DESIGN ENGINEER (AECG ASIC PD ENGINEER) THE ROLE : The position will involve working with a very experienced physical design team and is responsible for delivering the physical design of blocks/tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation chips in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 5-7 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

SMTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) T HE ROLE : As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. K EY RESPONSIBLITIES : Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Provide technical support to other teams P REFERRED EXPERIENCE : 12+ years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4

Job Description : Hands on experience in Block level PnR convergence with Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus In this position, candidate is expected to lead all block/chip level PD activities including floor plans, placement, CTS, optimization and routing techniques, RC extraction, STA, EM/IR DROP, PV Familiar with deep sub-micron designs below 10nm preferred BE/B Tech/ME/M TECH