401 Physical Verification Jobs - Page 5

Job Requirements 1. Lead High Performance ARM Core Hardening Job Title: Lead Engineer ARM Core Hardening Location: BLR/Hyd Experience: 812 years Technology Node: 5nm/3nm/2nm FinFET/GAA Reports To: Director/Technical Manager SoC Implementation Key Responsibilities: Lead end-to-end RTL-to-GDSII hardening of ARM Cortex-A/X/Neoverse cores (single and multi-cluster). Collaborate with RTL, CAD, DFT, low power, and architecture teams to define floorplan and implementation strategy. Own full flow: floorplanning, power planning (UPF-based), placement, CTS, routing, ECO, timing closure, physical verification, and signoff. Drive design quality metrics: PPA (Performance, Power, Area), DRC/LVS clean, IR drop, EM, and thermal-aware optimization. Architect physical implementation methodology tailored to ARM hardening: hierarchical flow, black-boxing strategy, physical partitioning, clocking architecture. Interface with foundry and EDA vendors for process tech enablement and tool issues. Technical Skills: Deep understanding of ARM core microarchitecture (pipeline, fetch/decode, FPU/NEON, L1/L2 cache). Expert in Synopsys/Cadence tools: ICC2/Fusion Compiler, Tempus/Innovus, Primetime, StarRC, RedHawk/Totem. Advanced clock tree design: CCOpt, custom H-trees, mesh, and multi-source CTS. Experience with UPF-based low power flows and Conformal Low Power (CLP) verification. Familiarity with physical-aware DFT and scan compression (test-mode aware synthesis/placement). Familiar with physical architecture trade-offs (voltage islands, power domains, channel management). Knowledge of EMIR, thermal, aging-aware closure in HPC-class cores. Experience taping out at 5nm or lower is mandatory. --- 2. Engineer ARM Core Hardening Job Title: Physical Design Engineer ARM Core Hardening Location: BLR/Hyd Experience: 38 years Technology Node: 5nm/3nm/2nm FinFET/GAA Key Responsibilities: Implement physical design of ARM core and subsystems from RTL to GDSII. Responsible for floorplanning, placement, CTS, routing, timing and physical closure of core logic. Perform static timing analysis, IR/EM validation, and physical verification. Optimize for frequency, leakage, and area within power and thermal budgets. Support integration of hardened cores into SoC top-level environment. Technical Skills: Good understanding of ARM core architecture and pipeline structure. Experience in Synopsys or Cadence PnR and signoff tools (ICC2, Fusion Compiler, Innovus, PT, RedHawk). Experience in UPF flows, CPF/UPF constraints, and low-power verification tools. Good in timing ECOs, DFT integration, scan reordering and hold fixing in low power designs. Strong debugging skills: congestion, IR drop, setup/hold, crosstalk, antenna, and DRC. Familiar with scripting (TCL, Python, Perl) to automate flows and reports. Work Experience Lead High Performance ARM Core Hardening Experience working with ARM POP (Processor Optimization Pack) or ARM Artisan Physical IP. Worked with multi-core cluster hardening and coherent interconnects (e. g. , CMN-600). Experience with RTL-based performance modeling and correlation with implementation ARM Core Engineer: ARM POP usage experience. Previous tapeout at \u22647nm. Exposure to hierarchical and multi-voltage designs. Familiarity with advanced floorplanning constraints for multi-core clusters.

Experience or strong interest in developing memory compilers, addressing layout-related issues, and ensuring optimization. Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout. Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc. Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area. Excellent hands-on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL. Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and deliveryExcellent communication skills and proactive at work. Excellent communication skills and proactive at work

1. Financial / Strategic Strategize and plan to create a robust secondary logistics function with an aim to drive overall effectiveness and efficiency, thereby positively impacting TLC (Total Logistics Cost) Engage and sustain relationships with high performing transporters for continuous and reliable and sustainable services thereby facilitating an edge over other competitors Prepare yearly budget for logistics department and share the same with the Logistics Head for approval Ensure adherence to the approved budget Take initiatives to drive growth for DCBL and ensure sustained growth in line with long-term and short-term objectives of the organization 2. Monitoring and Control Monitor and control all activities involving transportation, stock control and the flow of goods Monitor the secondary performance with respect to targets set by the Sales team, and take appropriate measures to prevent/correct fluctuations in target achievement Ensure timely uploading of freight on SAP and approve fluctuations as per analysis 3. Logistic Operations Ensure timely delivery of goods to the dealers / distributor shops thereby driving achievement of sales targets for DCBL Manage the transporter activities and ensure regular follow ups with them for timely transportation of material to customers Review the performance of transporters and share feedback with management for decision making. ensure association with high performing vendors for cost and service related benefits Implement new techniques and processes to drive overall cost effectiveness and efficiency of the function Utilize Logistics analysis being conducted by the Logistics analytics (role) and ensure decisions are made basis the insights. Drive reduction in Total Logistics cost, while maintaining high service levels. Ensure time and cost optimized rake planning to effectively reduce logistics cost Appoint C&Fs after carefully checking backgrounds, their associated network and also compare proposals Manage all operational matters pertaining to CNFs, their disputes, change of rates, union issues, etc. and address all queries / issues for smooth functioning of Secondary Logistics Function Ensure physical verification of stocks at warehouses by the regional team by dedicated surprise / special visits/ audits Ensure complete safety of logistics, including all systems, processes and personnel involved Ensure efficient and effective vendor management/agreement including driving key capability building initiatives for key vendors Ensure initiation and sensitization of the employees towards digitization and automation of the processes Focus on utilization of advanced business analytics tools to derive key insights critical for the success of the organization 4. Self/ Team Development Review and monitor performance of team members and provide requisite developmental support/ inputs Recommend training as required for teams development Develop the team and update their knowledge base to cater the organization need Strategize avenues for enhancing employee satisfaction in the function, resulting in high engagement levels of employees

The Store Assistant will work closely with the Store In-Charge to ensure the smooth operation of the store, manage inventory, and provide top-notch customer service. This role requires candidates with a background in electrical or mechanical parts and a proactive approach to tasks. Key Responsibilities: Assist the Store In-Charge in managing day-to-day store operations. Provide excellent customer service by helping with product inquiries and purchases. Maintain a clean, organized, and well-stocked store environment. Receive, unpack, label, and stock inventory, with a focus on electrical and mechanical components. Identify and handle manufacturing parts, ensuring proper follow-up on rejected parts with suppliers. Respond to supplier concerns promptly and professionally. Collaborate with the Store In-Charge and General Manager for work planning and arrangements. Skills and Competencies: Solid knowledge of electrical and mechanical parts and experience identifying manufacturing components. Ability to work independently, with agility in handling multiple tasks. Adaptable and prepared to manage challenges in a fast-paced work environment. Flexibility to work evenings, weekends, and holidays as required. Proficient in Microsoft Office (Excel, Word, etc.). Strong analytical skills to meet store requirements quickly. Capable of standing and walking for extended periods and lifting up to 15 kilograms. Qualifications: Diploma or ITI in Electrical or Mechanical field. Familiarity with electrical and mechanical components or manufacturing parts is preferred. Fluent in Hindi, English, and Kannada (local language proficiency preferred). Additional Requirements: Male candidates only . Immediate joiners or candidates with a maximum of 15 days notice period are preferred.

1. Costing related work Preparation of Cost sheet as per RFQ. Cost Estimate and Cost Run Activity Rate Working 2. MIS related work Consumption Analysis Report Inventory Reconciliation. Provision working of Inventory. 3. SAP SAP Experience. 4. Inventory related work Inventory valuation Physical verification of Stock Assistance to Auditors in Stock verification Input Output working. 5. Statutory Audit / Cost Audit completion on time 6. Fixed Assets Asset code creation Depreciation run Additions and deletion of assets Physical verification of assets Facilitating plant in cost reduction programme. Please send your updated CV with CTC details to - tejas.chavan@finolexjpower.com & rahul.jadhav@finolexjpower.com (BOTH)

Quest Global is a leading organization known for its innovation and rapid growth in the engineering services sector. With a rich domain expertise and a strong presence in the top OEMs across seven industries, we are a company with a 25-year legacy and a vision to reach a centennial milestone. Driven by ambition, passion, and humility, we are on a journey to shape the future through engineering. We are in search of individuals who embody the spirit of humble geniuses, believing in the power of engineering to turn the impossible into reality. Our ideal candidates are innovators inspired by technology and driven to design, develop, and test solutions as trusted partners for Fortune 500 clients. As a diverse team of engineers, we understand that our work goes beyond technical solutions; we are shaping a brighter future for all. If you are eager to contribute to meaningful projects and be part of an organization that values collective success and learning from failures, we invite you to join us. We are looking for achievers and courageous challenge-crushers who possess the following skills and characteristics: Responsibilities: - Performing floor-planning and routing studies at block and full-chip level - Executing top-level floorplan and clock pushdown to Partition - IO Planning and bump planning - Collaboration with Package team to meet Die file milestones - Conducting full chip and partition level timing analysis - Exploring low power techniques and power reduction opportunities - Designing and analyzing clock distribution - Executing Physical verification activities at full-chip level - Leading technical activities of physical design throughout technology readiness, design, and execution Qualifications: - Proficiency in Netlist2GDSII Implementation, including Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, and Chip finishing - Experience in Physical Design Methodologies and sub-micron technology of 16nm and lower nodes - Handling designs with >1M instance count and 1 GHz frequency - Programming skills in Tcl/Tk/Perl for automating design processes and enhancing efficiency - Hands-on experience with PNR Suite from Cadence & Synopsys (Innovus & ICC2) - Strong background in Static Timing Analysis (PrimeTime SI), EM/IR-Drop analysis (PT-PX, Redhawk), and Physical Verification (Calibre) Education Type: M.E/M.Tech/MS-VLSI Design & Embedded System Job Type: Full Time-Regular Experience Level: Mid Level Total Years of Experience: 5 - 8,

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: VLSI Physical Verification. Experience: 5-8 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Design Planning. Experience: 1-3 Years.

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: VLSI Physical Verification. Experience: 5-8 Years.

Manage all student progress and prepare required strategies to overcome issues. Arranging for guest lectures. Arranging visits to the local parlors for the students. Arranging Induction & different sessions too. Looking after placements for students of hub center Maintaining pre placement and post-placement data and sharing it with the central office. Checking the quality of training at the centers and submitting reports about the same. Taking an initiative in creating new placement partnerships and tie ups in coordination with the Central team. Track the students for the complete period of their employment in the city. Provide mentor-ship support to students employed in the region to help them settle down including counseling, helping with finding accommodation, resolving issues with employers, helping establish social network in city, providing any other emergency support in the city Capture feedback of students and recruiters on an ongoing basis. Build and maintain regular connections with current and past employers & clients. Requirements Willingness to travel regularly Minimum Qualification Graduation 1 years of experience in the field Own two wheeler with required documents Basic Computer knowledge (Microsoft Excel & Word, Internet, etc.) Good Communications Skills Fluency in English, Hindi & the Regional Language (Kannad) Experience/ interest in training, teaching & coordinating.

Key Responsibilities: Manage plant accounting for Faridabad and Dharuhera plants. Controlling plant profitability through financial analysis and cost controls. Fully implemented Ways of Working for all key monthly/quarterly/annual processes and reconciliations. Ensure timely and accurate submission of budget, strat plan, MIS and forecast as per agreed timeline Meeting Cash flow as per outlook / budget. No surprises for cash. Physical verification of Inventory on quarter basis and Fixed Assets on annual basis Lead Statutory and internal audits. Ensure timely closure of internal audit points Ensure no supplier overdue ageing > 90 days without specific reason. Standard Operating Processes (Blackline, Corporate audits, and Governance). Timely closure of corporate audit, internal audit and other audits along with open observations. People development in the function No customer overdue without specific reason. Qualification & Experience: CA must with 10-to-12-years experience. Specific Functional Capabilities, Knowledge and Skills: Knowledge of IND AS and IFRS Accounting. GST law & TDS/ TCS and various return filing under this law Knowledge of MIS & Budgeting Knowledge of Fixed Assets Register and Depreciation Knowledge of Import/ export accounting Knowledge of ERP software

We are seeking a Warehouse Supervisor with experience in the food industry to oversee critical warehouse operations, ensuring timely and efficient handling of goods, container loading, and material movement across the facility. The ideal candidate

Job Purpose Our company is looking for an experienced Dy Manager (Accounts) who will be responsible for- Day to day review of accounts. Review and analyse Quarterly and Annual Accounts Reports before submission to CFD team. Co-ordination and submission of data to Statutory auditors Internal Auditor. Physical verification of stocks & assets as per the schedule timeline. Driving other projects like Solar power, VPPA, RPO which adding value to the unit. Adherence to payment process flow and comply with group policies. Effective fund management for domestic and foreign payment. Direct Tax Compliance: Timely and Effective Compliance of Direct taxation. Day to day update on new changes with respect to direct tax compliance and implement it on applicable area. Submission of data to CFD as per stipulated timeline and ensure Audit without any query. Involve in Completion of Tax Audit & Income Tax Assessment. Preparation of various details required for finalization. Co-ordination with other Department and within Department to ensure that the Balance Sheet is prepared as per requirement and in stipulated time Specific Skill Set: 1. Quick learner with the ability to handle multiple tasks simultaneously, maintain focus, and adapt to a variety ofchallenges 2. Good written and verbal communication skills 3. Strong sense of time organization and urgency & able to work independently and within a team

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 4 years of experience with physical design flow such as floor planning, place and route, or physical verification. Experience with low-power design techniques, such as power gating, clock gating, or voltage scaling. Preferred qualifications: Experience in using Machine Learning (ML) in physical design. Knowledge of machine learning algorithms from logistic regression to deep neural networks and reinforcement learning. Knowledge of data structures and algorithms. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will contribute to improving Power Performance Area (PPA) using machine learning techniques. You will use the experience of physical design and machine learning to solve technical problems and improve on Power, Performance, Area and Schedule. You will work on design and optimizations, floorplan, place and route, clock and power planning, timing analysis, and Power Delivery Network (PDN) analysis. You will collaborate across Alphabet working with design, CAD and machine learning teams. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Deploy Artificial Intelligence (AI) solutions into chip design, work with internal teams, Google DeepMind and other teams to explore solutions and apply to improve chip design PPA or cycle time.

Job Description Physical verification and readiness of equipment and instrument for process. Arranging the process accessories and consumables in process area before batch execution. Coordination for dispensing of raw material required for the production processes. Preparation of process, equipment and area related SOPs and EOP s. Preparation of process, area and equipment qualification/ validation protocols. Preparation and execution of various reports like process, equipment, area qualification and validation. Request and Issuance of BPR. Preparation and review of BPR. Preparation and execution of study protocols, URS as and when required Work Experience 4 to 7 Years in Downstream processing. Education Masters in Biotechnology or Biochemistry B. Tech in Biotechnology or Biochemistry Competencies

Principal Physical Design Engineer in Pune, MH, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: Ampere Computing is seeking a highly skilled engineer to join our physical design team with a focus on both CPU/GPU physical design and interconnect integration/implementation for CPU and GPU products. This role requires deep expertise in high-speed and power efficient physical design and methodologies with hands-on experience implementing CPU/GPU & interconnect networks to deliver robust, high-performance silicon solutions. You will collaborate closely with Architects, RTL designers, packaging team, and timing, power & DFT teams to ensure robust, high-performance designs that meet stringent timing, power, and area requirements. Interconnect floor planning iterations, partitioning, pin-placement, wire planning, clock distribution network. Working with Architecture, RTL and timing teams for optimal floorplan from system performance point of view. Implement power and clock domain crossing with UPF and timing methodologies. Converge timing on high speed interface with appropriate methods of clock balancing and skewing. Lead and execute physical design tasks for CPU/GPU blocks including floor planning, placement, clock tree synthesis, routing, and optimization. Collaborate with RTL designers and timing engineers to achieve timing closure, power targets, and area goals. Perform physical verification and signoff checks ensuring design compliance with foundry rules and design specifications. Analyze and resolve physical design issues such as congestion, timing violations, and signal integrity challenges. Develop scripts and automation flows to improve design efficiency and quality. Address interconnect-related challenges such as crosstalk, IR drop, electromigration, and noise. Document design methodologies, best practices, and integration guidelines specific to Ampere s CPU/GPU physical design flows. Collaborate and work with cross geo teams in India & Vietnam About you: M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience Experience in high performance/low power physical design, preferably with a focus on CPU and/or GPU architectures. Proven expertise in both CPU / High performance physical design and interconnect integration/implementation. Solid understanding of timing analysis, signal integrity, power integrity, electromigration, and advanced process technologies (7nm, 5nm, or below). Deep understanding of semiconductor device physics, interconnect materials, and advanced process technologies (7nm, 5nm, or below). Strong proficiency with EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Calibre, and parasitic extraction tools (StarRC, Quantus). Experience with scripting languages (Tcl, Python) for automation and tool customization. Excellent problem-solving skills and ability to work effectively in cross-functional teams. Effective communication skills to collaborate with design, verification, and manufacturing teams. What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Principal Physical Design Engineer in Bangalore, KA, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: Ampere Computing is seeking a highly skilled engineer to join our physical design team with a focus on both CPU/GPU physical design and interconnect integration/implementation for CPU and GPU products. This role requires deep expertise in high-speed and power efficient physical design and methodologies with hands-on experience implementing CPU/GPU & interconnect networks to deliver robust, high-performance silicon solutions. You will collaborate closely with Architects, RTL designers, packaging team, and timing, power & DFT teams to ensure robust, high-performance designs that meet stringent timing, power, and area requirements. Interconnect floor planning iterations, partitioning, pin-placement, wire planning, clock distribution network. Working with Architecture, RTL and timing teams for optimal floorplan from system performance point of view. Implement power and clock domain crossing with UPF and timing methodologies. Converge timing on high speed interface with appropriate methods of clock balancing and skewing. Lead and execute physical design tasks for CPU/GPU blocks including floor planning, placement, clock tree synthesis, routing, and optimization. Collaborate with RTL designers and timing engineers to achieve timing closure, power targets, and area goals. Perform physical verification and signoff checks ensuring design compliance with foundry rules and design specifications. Analyze and resolve physical design issues such as congestion, timing violations, and signal integrity challenges. Develop scripts and automation flows to improve design efficiency and quality. Address interconnect-related challenges such as crosstalk, IR drop, electromigration, and noise. Document design methodologies, best practices, and integration guidelines specific to Ampere s CPU/GPU physical design flows. Collaborate and work with cross geo teams in India & Vietnam About you: M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience Experience in high performance/low power physical design, preferably with a focus on CPU and/or GPU architectures. Proven expertise in both CPU / High performance physical design and interconnect integration/implementation. Solid understanding of timing analysis, signal integrity, power integrity, electromigration, and advanced process technologies (7nm, 5nm, or below). Deep understanding of semiconductor device physics, interconnect materials, and advanced process technologies (7nm, 5nm, or below). Strong proficiency with EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Calibre, and parasitic extraction tools (StarRC, Quantus). Experience with scripting languages (Tcl, Python) for automation and tool customization. Excellent problem-solving skills and ability to work effectively in cross-functional teams. Effective communication skills to collaborate with design, verification, and manufacturing teams. What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Job Title: AI/ML Engineer - Time Series Forecasting & Clustering Location: Bangalore Experience: 2+ Years Job Type: Full-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting : Build models to predict trends from time series data. Clustering : Develop algorithms to group and analyze data segments. Data Insights : Analyze data to enhance model performance. Team Collaboration : Work with teams to integrate models into products. Stay Updated : Apply the latest AI techniques to improve solutions. Qualifications: Education : Bachelors/Masters in Computer Science or related field. Experience : Hands-on experience with time series forecasting and clustering. Skills : Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and Wellness: Healthcare policy covering your family and parents. Food: Enjoy scrumptious buffet lunch at the office every day. Professional Development: Learn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and Recognitions: Recognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto? Health & Family: Comprehensive benefits for you and your loved ones, ensuring well-being. Growth Mindset: Continuous learning opportunities to stay ahead in your field. Dynamic & Inclusive: Vibrant culture fostering collaboration, creativity, and belonging. Career Ladder: Internal promotions and clear path for advancement. Recognition & Rewards: Celebrate your achievements and contributions. Work-Life Harmony: Flexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelor’s or Master’s degree from a top-tier institute. 5+ years of experience in STA/Timing from product-based companies. Job : STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience 7 to 15 years Physical design of block level with full understanding of PnR cycle. Good understanding of Physical design fundamentals Good hands-on experience on industry standard pnr tools like ICC2/Innovus Good understanding on signoff tool like Prime time , Redhawk and calibre Should be able to guide junior engineers in resolving technical issues. Tools ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS ScriptingTCL, Perl

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 2+ years Hardware Engineering experience or related work experience. 2+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 3+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelors or master’s in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools – Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages – , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational RequiredBachelor's, Electrical Engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm