401 Physical Verification Jobs - Page 4

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Responsibilities: 5 to 10 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Additional Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing ]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 12+ years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Qualcomm India Private Limited is a leading technology innovator that aims to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should possess strong analytical and technical skills, especially in ASIC design. Responsibilities for this position include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be expected to create design experiments, conduct detailed PPA comparison analysis, collaborate with various teams for optimization, and develop Place & Route recipes for optimal PPA results. Qualifications required for this role include 6-15 years of experience in High-Performance core Place & Route and ASIC design Implementation. Preferred qualifications involve extensive experience in Place & Route with FC or Innovus, knowledge of complete ASIC flow with optimization techniques, proficiency in STA using Primetime and/or Tempus, and skills in Perl/Tcl, Python, C++, among others. Problem-solving abilities, experience with CPU micro-architecture, low power implementation techniques, and clock tree implementation techniques are also desired. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can contact Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised that only individuals seeking a job at Qualcomm should use the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

You should possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, including tasks such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. It is essential to have experience with Physical Design Methodologies and sub-micron technology, particularly in 16nm and lower technology nodes. Moreover, you should have expertise in Analog and Mixed Signal Design and be familiar with handling designs with more than 5M instance count and operating at a frequency of 1.5GHz. Proficiency in programming languages such as Tcl, Tk, and Perl is required to automate the design process and enhance efficiency. Hands-on experience with PnR Suite from Cadence & Synopsys, specifically Innovus & ICC2, is a must. Additionally, you should have a strong background in Static Timing Analysis using tools like PrimeTime for SI analysis, EM/IR-Drop analysis with PT-PX and Redhawk, as well as Physical Verification using Calibre. Understanding the practical application of methodologies, Physical Design Tools, Flow Automation, and driving improvements in these areas is highly beneficial. Experience in complex SOC integration, Low Power and High-Speed Design, as well as proficiency in Advanced Physical Verification Techniques, are desirable skills for this role.,

Note - Alternate Saturdays' half day working (1st, 3rd & 5th) Key Roles & Responsibilities: Develop and maintain a fixed asset register that accurately reflects the company's fixed assets Establish and maintain procedures for recording and tracking fixed assets Ensure all new fixed assets are properly recorded and tracked in the register Ensure all disposals of fixed assets are properly recorded and tracked in the register Monitor and review the accuracy and completeness of the fixed asset register Calculate and record depreciation expense for all fixed assets Develop and maintain a system of internal controls to safeguard fixed assets Conduct regular physical inspections of fixed assets to verify their location and condition Prepare reports on the status of fixed assets, including their value and depreciation Assist with the preparation of financial statements by providing accurate and timely information on fixed assets Coordinate with other departments, such as finance and operations, to ensure the accuracy and completeness of fixed asset data Skills & Qualification Required: Bachelor's degree in accounting, finance, or a related field 3+ years of experience in fixed asset accounting or related field Strong knowledge of accounting principles and standards Experience with fixed asset management software preferred

Senior Staff Engineer - Analog Layout Hyderabad, Telangana, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10892 Remote Eligible No Date Posted 14/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a deep understanding of Analog and Mixed Signal Circuit Layout. With a minimum of 9 years of experience, you bring a strong background in transistor-level analog and mixed-signal layout design. You possess extensive knowledge in CMOS and FINFET technologies, and your expertise in semiconductor device physics sets you apart. Your problem-solving skills are top-notch, and you are detail-oriented, self-directed, and passionate about learning new techniques. You are adept at communicating effectively with cross-functional teams to ensure successful project execution. You thrive in a dynamic environment and are excited about the opportunity to contribute to cutting-edge technology that drives the future. What You ll Be Doing: Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment. Collaborate with cross-functional teams to ensure successful project execution. Create and review layout documents to ensure they meet quality standards and are delivered on time. Support the team in troubleshoot physical verification issues to achieve clean and desired results Device level floorplan, placement, routing, and physical verification of all critical high-speed blocks Design and development of transistor-level Analog and mixed-signal layout as per project needs The Impact You Will Have: You will drive the Layout design of the project from Floorplan, design and development till the project release. You will drive the Layout design of the project from Floorplan till the project release and lead the project throughout the entire design and development phase. Strong Knowledge and experience in layout design of high-speed blocks in latest Tech Nodes (2nm, 3nm, 5nm) You will drive the design and development of high-quality analog and mixed-signal layouts. Your expertise will ensure the successful implementation of CMOS and FINFET technologies. Through effective troubleshooting, you will contribute to achieving clean physical verification results. Your attention to detail will ensure that layout documents meet quality standards and deadlines. By managing project schedules and milestones, you will help deliver projects on time. Your collaboration with cross-functional teams will enhance project success and innovation What You ll Need: Bachelors or Masters degree in Electrical Engineering or a related field. Minimum 9+ years of experience in Analog and Mixed Signal Circuit Layout. Proficiency in Analog Layout Flow from device placement to GDS release. Strong knowledge of CMOS and FINFET technologies and semiconductor device physics. Experience with EDA tools for custom mixed-signal layout flows. Understanding of CMOS fabrication technology and deep sub-micron effects on layout. Knowledge of electro-migration, reliability concepts, and ESD/LUP concepts as applied to layout. Passion for learning and exploring new techniques. Who You Are: A proactive leader with excellent communication and mentoring skills. Detail-oriented and committed to delivering high-quality results. Innovative and capable of driving technological advancements. Collaborative and able to work effectively with cross-functional teams. A problem-solver with strong analytical skills. The Team You ll Be A Part Of: You will be part of a dynamic and innovative layout design team focused on creating high-performance analog and mixed signal layouts. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organizations goals. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Senior Engineer - Standard Cell Layout Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12161 Remote Eligible No Date Posted 14/07/2025 Senior Standard Cell Layout Engineer Standard Cell Layout Designer Digital Layout Engineer We Are: You Are: You are an experienced and highly motivated professional with a robust technical background in standard cells layout design. Your passion for excellence and precision drives you to create layouts that set the standard for quality and manufacturability. You thrive in collaborative, cross-functional environments, seamlessly working with circuit designers, verification engineers, and other stakeholders to deliver optimized layout solutions. Your expertise in industry-leading EDA tools such as Cadence Virtuoso or Synopsys Custom Compiler enables you to tackle complex digital circuit layouts with efficiency and accuracy. Your systematic approach and strong problem-solving skills allow you to navigate technical challenges with ease, always seeking innovative ways to enhance design methodologies and best practices. You are deeply familiar with physical verification processes and design rule checks, ensuring that every layout you deliver meets stringent quality and manufacturability standards. Your curiosity and commitment to lifelong learning keep you updated on the latest advancements in standard cell layout design, making you an invaluable resource for your team. You communicate effectively, embrace feedback, and are eager to contribute to a culture of continuous improvement and shared success . What You ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for digital circuits, ensuring alignment with project goals and timelines. Create and optimize complex standard cell layouts using industry-standard EDA tools such as Cadence Virtuoso or Synopsys Custom Compiler. Perform thorough physical verification and design rule checks (DRC/LVS) to guarantee design integrity and manufacturability. Work closely with circuit designers to understand design specifications, constraints, and performance targets, translating them into robust layouts. Contribute to the development, documentation, and refinement of layout design methodologies, flows, and best practices within the team. Remain up to date with industry trends, emerging technologies, and advancements in standard cell layout design, sharing knowledge with peers. The Impact You Will Have: Deliver high-quality layout designs that form the foundation of Logic Libraries IP development, essential for advanced SOC subsystems. Drive innovation in layout design methodologies, contributing to Synopsys leadership in the industry. Ensure that all designs meet or exceed manufacturability and reliability standards, reducing risk and time-to-market for key products. Collaborate effectively with circuit designers and verification teams to meet challenging design specifications and project milestones. Contribute to the overall success and reputation of the Logic Libraries IP group through your technical excellence and teamwork. Mentor and support junior team members, fostering a culture of knowledge-sharing and continuous improvement. What You ll Need: Bachelor s or master s degree in electronics engineering or a related field. Minimum2 years of hands-on experience in standard cells layout design for digital circuits. Proficiency with industry-standard EDA tools, including Cadence Virtuoso or Synopsys Custom Compiler. Deep knowledge of layout design methods, techniques, and methodologies for high-performance and robust standard cells. Experience with physical verification tools such as ICC2, including DRC and LVS checks. Strong analytical and systematic problem-solving skills, with a detail-oriented mindset. Ability to work effectively in a collaborative, team-driven environment. Excellent communication and interpersonal skills, with a willingness to learn and share knowledge. Who You Are: A collaborative team player who values open communication and shared goals. Detail-oriented, with a commitment to delivering high-quality and reliable work. Curious and proactive, embracing continuous learning and professional development. Adaptable and resilient in the face of technical challenges and evolving requirements. Passionate about innovation, with a drive to improve processes and methodologies. Self-motivated, organized, and able to manage multiple priorities in a fast-paced environment. The Team You ll Be A Part Of: You ll join a dynamic and supportive Logic Libraries IP group focused on developing state-of-the-art standard cell libraries for advanced SOC subsystems. Our team thrives on collaboration, innovation, and technical excellence. We value diverse perspectives and foster an inclusive environment where every member s contributions are recognized and celebrated. Together, we drive the success of Synopsys IP solutions, setting industry benchmarks and enabling our customers to achieve next-generation performance . Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll Do: Perform hands-on physical design and physical verification tasks across projects in advanced process nodes. Manage project-specific ASIC development flow setup and maintenance. Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities. Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database. Ensure correct IP and pad-ring integration in block and flat designs. Mentor junior PD/PV team members and oversee their tasks. You will be reporting to ASIC Design Director. What Youll Need: Minimum 8+ Years of experience in ASIC/ SoC Physical Design. Skills - have working experience in advanced FinFET node designs. Experience with Cadence PnR/STA tools and Calibre; good scripting/automation skills is a must. Education - B. Tech /M. Tech in Electronics Engineering. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers. Medical Insurance and a cohort of Wellness Benefits Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Select with space bar to view the full contents of the job information. Accounting Assistant Job Details | Valvoline Global Search by Keyword Search by Location Work Location Type Select how often (in days) to receive an alert: Select how often (in days) to receive an alert: Accounting Assistant Date: Jul 14, 2025 Location: Gurgaon, HR, IN, 122016 Work Location Type: Description: Why Valvoline Global Operations? At Valvoline Global Operations , we re proud to be The Original Motor Oil , but we ve never rested on being first. Founded in 1866, we introduced the world s first branded motor oil, staking our claim as a pioneer in the automotive and industrial solutions industry. Today, as an affiliate of Aramco , one of the world s largest integrated energy and chemicals companies, we are driven by innovation and committed to creating sustainable solutions for a better future. With a global presence, we develop future-ready products and provide best-in-class services for our partners around the world. For us, originality isn t just about where we began; it s about where we re headed and how we ll lead the way. We are originality in motion. Our corporate values Care, Integrity, Passion, Unity, and Excellence are at the heart of everything we do. These values define how we operate, how we treat one another, and how we engage with our partners, customers, and the communities we serve. At Valvoline Global, we are united in our commitment to: Treating everyone with care. Acting with unwavering integrity. Striving for excellence in all endeavors. Delivering on our commitments with passion. Collaborating as one unified team. When you join Valvoline Global , you ll become part of a culture that celebrates creativity, innovation, and excellence. Together, we re shaping the future of automotive and industrial solutions. As an Accounting Assistant, you will be working for the India Finance team. Handling the activities mainly for Concur and export invoice processing and record retention, fixed asset physical verification. Additionally, this role will also be involved the processing of Ad-hoc treasury related requests such as banking requests and documentation etc. This hybrid role combines on-site work in Gurgaon, India , with 2 days of remote work per week, operating from 9 AM to 6 PM IST. How You ll Make an Impact Create and monitor a system of controls, procedures, and forms for the recording of fixed assets and physical verification of the same Preparation of export invoices , record keeping all EBRC s and foreign inward remittances Update the SOPs/work instructions if there is any change or modification in the procedure Prepare sales register and assist the auditors in their queries Review and processing of all concur reimbursements for employees related to travel, telephone and others across multiple entities Treasury related documentation preparation and support for banking with both BOA and HDFC Other duties and responsibilities as determined by Valvoline from time to time in its sole discretion Primary Interactions - Internal and External Entire finance function, Country Controllers India /APAC, SAP Support team (Internal) External Auditors (External) only on specific cases as per requirement What You ll Need Bachelors degree in Accounting. MBA Preferred 3-5 years of relevant accounting experience in a multinational environment or shared services center What Will Set You Apart Must have good level of knowledge related to accounting practices Must have excellent Analytical & reasoning Skills Must have SAP working knowledge for accounting module Ability to do proper root cause analysis wherever applicable Experience with Indian and International Accounting Standards Experience in the use and application of SAP systems Excellent understanding of the use and application of other IT software (Excel, Word) Pro-active & should take self-initiative, detail oriented, self-motivated and team player Good & Effective Communication Skills (both verbal and written) Should be flexible for working in shifts , and from office or hybrid as per need Valvoline Global is an equal opportunity employer . We are dedicated to fostering an environment where every individual feels valued, respected, and empowered to contribute their unique perspectives and skills. We strictly prohibit discrimination and harassment of any kind, regardless of race, color, religion, age, sex, national origin, disability, genetics, veteran status, sexual orientation, gender identity, or any other legally protected characteristic. We are committed to ensuring accessibility throughout our recruitment process. for accommodation requests. For inquiries about application status, please use the appropriate channels listed in your application materials. Are You Ready to Make an Impact? At Valvoline Global, we re looking for passionate and talented individuals to join our journey of innovation and excellence. Are you ready to shape the future with us? Apply today. Requisition ID: 1617

As a Layout Design Engineer at Micron Technology, you will play a crucial role in developing critical analog, mixed-signal, and custom digital blocks. Your responsibilities will include designing and developing layout designs, performing layout verification such as LVS/DRC/Antenna, conducting quality checks, and providing support documentation. It will be your responsibility to ensure timely delivery of block-level layouts with acceptable quality while taking ownership of area estimation, scheduling, and execution to meet project deadlines. Collaboration with team members and being a supportive team player are essential aspects of this role. To be successful in this position, you should have 2 to 5 years of experience in analog/custom layout design in advanced CMOS and FinFET processes across various technologies and foundries ranging from 16nm to 130nm. Proficiency in tools like Cadence Virtuoso GXL/XL and DRC/LVS/Extraction (Cadence/Mentor Graphics/Synopsys) is a must. Hands-on experience in creating layouts of critical blocks such as LDO, Bandgap, Ref Generators, and Oscillator is required. A strong understanding of Analog Layout fundamentals, including Matching, Electromigration, Latch-up, coupling, crosstalk, IR-drop, and active/passive parasitic devices, is essential. You should also possess the ability to comprehend design constraints and implement high-quality layouts. Problem-solving skills in physical verification (LVS/DRC/Antenna/PEX) of custom layouts and knowledge of scripting languages like Skill, Python, Perl, TCL, SVRF, etc., will be beneficial. A passion for continuous learning, innovation, success, and teamwork is highly valued in this role. Micron Technology, Inc., is a global leader in memory and storage solutions, dedicated to transforming how information enriches lives worldwide. With a focus on technology leadership, operational excellence, and customer satisfaction, Micron offers a wide range of high-performance DRAM, NAND, and NOR memory and storage products under the Micron and Crucial brands. The innovative solutions developed by Micron's talented workforce drive the data economy, enabling advancements in artificial intelligence and 5G applications across various platforms. If you are excited about contributing to cutting-edge technology and being part of a dynamic team at Micron Technology, please visit micron.com/careers for more information. For assistance with the application process or to request reasonable accommodations, please reach out to hrsupport_india@micron.com. Micron Technology strictly prohibits the use of child labor and adheres to all relevant laws, regulations, and international labor standards.,

Any Graduate with good comm skills Min 5+ yrs of expn in Stores & Inventory Management. Good at Stores Operations / Mutiple materials mgmt / Stock taking / Inventory Control / ERP / Excel /Email / GRN etc. Location : Chennai.

1. Financial / Strategic Strategize and plan to create a robust secondary logistics function with an aim to drive overall effectiveness and efficiency, thereby positively impacting TLC (Total Logistics Cost) Engage and sustain relationships with high performing transporters for continuous and reliable and sustainable services thereby facilitating an edge over other competitors Prepare yearly budget for logistics department and share the same with the Logistics Head for approval Ensure adherence to the approved budget Take initiatives to drive growth for DCBL and ensure sustained growth in line with long-term and short-term objectives of the organization 2. Monitoring and Control Monitor and control all activities involving transportation, stock control and the flow of goods Monitor the secondary performance with respect to targets set by the Sales team, and take appropriate measures to prevent/correct fluctuations in target achievement Ensure timely uploading of freight on SAP and approve fluctuations as per analysis 3. Logistic Operations Ensure timely delivery of goods to the dealers / distributor shops thereby driving achievement of sales targets for DCBL Manage the transporter activities and ensure regular follow ups with them for timely transportation of material to customers Review the performance of transporters and share feedback with management for decision making. ensure association with high performing vendors for cost and service related benefits Implement new techniques and processes to drive overall cost effectiveness and efficiency of the function Utilize Logistics analysis being conducted by the Logistics analytics (role) and ensure decisions are made basis the insights. Drive reduction in Total Logistics cost, while maintaining high service levels. Ensure time and cost optimized rake planning to effectively reduce logistics cost Appoint C&Fs after carefully checking backgrounds, their associated network and also compare proposals Manage all operational matters pertaining to CNFs, their disputes, change of rates, union issues, etc. and address all queries / issues for smooth functioning of Secondary Logistics Function Ensure physical verification of stocks at warehouses by the regional team by dedicated surprise / special visits/ audits Ensure complete safety of logistics, including all systems, processes and personnel involved Ensure efficient and effective vendor management/agreement including driving key capability building initiatives for key vendors Ensure initiation and sensitization of the employees towards digitization and automation of the processes Focus on utilization of advanced business analytics tools to derive key insights critical for the success of the organization 4. Self/ Team Development Review and monitor performance of team members and provide requisite developmental support/ inputs Recommend training as required for team s development Develop the team and update their knowledge base to cater the organization need Strategize avenues for enhancing employee satisfaction in the function, resulting in high engagement levels of employees

Job Requirements Job Purpose: The role requires the incumbent to lead and improve the Receipt operations of the Spare Parts Warehouse by effectively coordinating and supervising activities. This entails a deep understanding and evaluation of daily KPIs and deliverables to ensure full compliance with service levels and maintain operational consistency, aiming for operational excellence and efficiency. Position Overview: Location: Chennai Position Title: Receipt Operations Reports to : Manager - CWH INBOUND OPERATIONS Function: Spare Parts Business What youll do: Monitoring and driving, Receipts shift operations according to KPIs Effective deployment of bay management and vehicle unloading strategies compared to turnaround time (TAT). Conduct a manual count of all parts or employ a weighing machine, verifying that each SKU carries an Approvedidentification tag as per RE. Upon receipt, no damages, discrepancies, incomplete deliveries, shortages, or incorrect prepacking of sticker parts are to be ensured. Gate entry, GRN management, and gate exist in alignment with the specified turnaround time. Promptly engage with the Receipt Quality Control team (RQC) and quickly clear Goods Receipt Notes (GRNs) along with productivity. Ensure that the parts in the staging area are stacked correctly Update the photo master with images of received new parts and ensure that all SKUs are accurately maintained with part no correctness. Extensive tracking of Goods in Transit (GIT) sections and their closure process. Manage vendor-rejected parts and resolve mother plant discrepancies on time (TAT) An audit will be conducted on the receipts for prepacked items. Transfer posting of Packed/unpacked items for timely posting and handed over to the Inventory team for binning Ensuring physical verification of stock against the system stock Ensuring the precise management of documents. Timely preparation of Management Information System reports. Ensuring 5S management, visual controls, and organizing Kaizens/Housekeeping. What youll bring: Experience: 2 to 5 years of experience in Automobile parts warehousing Qualification: BE/BTECH Mechanical, Automobile Ready to Join Us Apply via our website today. Join our trailblazing team and be a part of our legacy! So why waitJoin us and experience the freedom of embracing the road, riding with pure motorcycling passion.

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You are a seasoned professional with a deep understanding of Analog and Mixed Signal Circuit Layout. With a minimum of 6 years of experience, you bring a strong background in transistor-level analog and mixed-signal layout design. You possess extensive knowledge in CMOS and FINFET technologies, and your expertise in semiconductor device physics sets you apart. Your problem-solving skills are top-notch, and you are detail-oriented, self-directed, and passionate about learning new techniques. You are adept at communicating effectively with cross-functional teams to ensure successful project execution. You thrive in a dynamic environment and are excited about the opportunity to contribute to cutting-edge technology that drives the future. What you'll Be Doing: Design and development of transistor-level analog and mixed-signal layout. Device level floorplan, placement, routing, and physical verification. Troubleshoot physical verification issues to achieve clean and desired results. Create and review layout documents to ensure they meet quality standards and are delivered on time. Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones in a multi-project environment. Collaborate with cross-functional teams to ensure successful project execution. The Impact You Will Have: You will drive the design and development of high-quality analog and mixed-signal layouts. Your expertise will ensure the successful implementation of CMOS and FINFET technologies. Through effective troubleshooting, you will contribute to achieving clean physical verification results. Your attention to detail will ensure that layout documents meet quality standards and deadlines. By managing project schedules and milestones, you will help deliver projects on time. Your collaboration with cross-functional teams will enhance project success and innovation. What you'll Need: Bachelors or Masters degree in Electrical Engineering or a related field. Minimum 6 years of experience in Analog and Mixed Signal Circuit Layout. Proficiency in Analog Layout Flow from device placement to GDS release. Strong knowledge of CMOS and FINFET technologies and semiconductor device physics. Experience with EDA tools for custom mixed-signal layout flows. Understanding of CMOS fabrication technology and deep sub-micron effects on layout. Knowledge of electro-migration, reliability concepts, and ESD/LUP concepts as applied to layout. Passion for learning and exploring new techniques. Who You Are: Detail-oriented and self-directed with excellent problem-solving skills. Strong communication skills for effective collaboration with cross-functional teams. Ability to manage multiple projects and meet deadlines effectively. Innovative thinker with a passion for technological advancement. Team player who thrives in a dynamic and fast-paced environment.

Skills requried: • In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes. - Should have experience in Analog and Mixed Signal Design • Should have experience in handling >5M instance count , 1.5GHz frequency designs . • Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. • Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2) • Strong experience on Static Timing Analysis (PrimeTime - SI) , EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). • Understanding the practical application of methodologies and Physical Design Tools, Flow Automation, and Improvements. • Experience in complex SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techniques.

As a Layout Design Engineer at Micron Technology, you will be responsible for the design and development of critical analog, mixed-signal, and custom digital blocks. Your role will involve performing layout verification tasks such as LVS/DRC/Antenna checks, ensuring quality, and supporting documentation. It will be crucial for you to deliver block-level layouts on time with acceptable quality, taking ownership of area estimation, scheduling, and execution to meet project deadlines. Collaboration with team members and being a strong team player are essential aspects of this role. To qualify for this position, you should have 2 to 5 years of experience in analog/custom layout design in advanced CMOS and Finfet processes across various technologies and foundries ranging from 16nm to 130nm. Expertise in tools like Cadence Virtuoso GXL / XL and DRC / LVS / Extraction (Cadence / Mentor Graphics / Synopsys) is a must. Hands-on experience in creating layouts of critical blocks such as LDO, Bandgap, Ref Generators, Oscillator, etc., is required. A solid understanding of Analog Layout fundamentals and their impact on circuit performance is essential. You should be capable of implementing high-quality layouts while considering design constraints and solving physical verification challenges effectively. Moreover, familiarity with scripting languages such as Skill, Python, Perl, TCL, SVRF, etc., is beneficial for this role. A passion for continuous learning, innovation, success, and teamwork will drive your success as part of our dynamic team. Micron Technology, Inc. is a global leader in memory and storage solutions, committed to transforming how information enriches life for all. Our focus on customers, technology leadership, operational excellence, and product innovation sets us apart in the industry. Through our Micron and Crucial brands, we deliver a diverse portfolio of high-performance DRAM, NAND, and NOR memory and storage products that power the data economy, enabling advancements in artificial intelligence and 5G applications. To explore career opportunities with Micron Technology, please visit micron.com/careers. For any assistance with the application process or to request reasonable accommodations, please reach out to hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all relevant laws, rules, regulations, and international labor standards.,

We are looking for a highly skilled and experienced Memory Layout Engineer to join our team. As a Memory Layout Engineer, you will be responsible for designing and integrating layouts for advanced memory blocks across leading-edge process technologies. Your role will involve developing and verifying memory compilers with a strong focus on ultra-deep sub-micron layout challenges. Key Responsibilities: Memory Building Block Layout Design: - Designing layouts for essential memory components including Control and Digital logic, Sense amplifiers, Bit-cell arrays, and Decoders. Process Technology Expertise: - Working with advanced process nodes such as 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, and FinFET technologies. Physical Verification: - Developing memory compilers, addressing layout-related issues, and ensuring optimization. - Proficiency in Routing Congestion, Physical Verification in Custom Layout. - Knowledge of verification checks like DRC, LVS, ERC, Antenna, LPE, DFM, etc. - Understanding of analog layout techniques and circuit principles affected by layouts. Tools Experience: - Hands-on experience with industry-standard layout and verification tools in a Linux environment, including Cadence and Mentor EDA tools. Proficiency in VirtuosoXL. Leadership and Communication: - Demonstrated leadership skills to mentor and guide team members in layout execution. - Excellent communication skills and proactive work approach. Qualifications: - BTECH/MTECH - Minimum 3+ years of experience Location: - Bangalore / Hyderabad / Noida This role presents an exciting opportunity to work with cutting-edge technologies and collaborate with a team of experts. If you are passionate about memory layout design and enjoy working in an innovative environment, we encourage you to apply.,

You should have at least 3+ years of relevant experience in SoC Physical design, with a focus on multiple technology nodes including 5nm for TSMC and other foundries. Your expertise should include hands-on P&R skills, particularly in ICC/Innovus. You must possess expert knowledge in all aspects of Physical Design (PD) from Synthesis to GDSII, with a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Experience in taping out multiple chips and working at the top level in the latest technology nodes will be highly beneficial. Collaboration with CAD, Methodology & IP teams for PD implementation is critical, requiring regular sync-ups for deliveries. You should have significant knowledge, and preferably hands-on experience, in SoC STA, Power, Physical Verification, and other sign-off processes. Problem-solving capabilities, proactive attitude, hardworking nature, and strong interpersonal skills are essential for this role. A Bachelor's Degree in Electrical, Electronics, or Computer Engineering is required for this position. About Company: 7Rays Semiconductor Private Ltd. provides end-to-end custom SoC design solutions, including SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. The company focuses on offering services to top semiconductor and system companies to assist them in designing complex SoCs. The company believes in building effective partnerships with clients to deliver high-quality solutions tailored to their needs. With a dedicated engineering team and a successful track record in project execution, the company is committed to excellence and innovation in SoC Design, Development, and deployment of customers" products.,

Leading MNC company into IT domian looking for IT Asset Manager Asset Movement Asset Reservations Asset Disposal Periodic Physical Verification Maintain hardware asset database to ensure completeness and accuracy at all times Ensure that IT Asset Management SLAs and KPIs are met at all the time Reconciliation of discovered assets that are not tracked in the asset management database Manage the validation of the asset management database records by performing a scheduled task to QA the data for asset records Review existing Asset Management process and suggest improvements in process efficiencies and controls Manage spares and provide inputs for timely procurement of necessary spares to manage repair maintenance activities. Track movement of assets from one location to another Location: Delhi,Mumbai,Pune,Bengaluru

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

The position will involve working with a very experienced physical design team and is responsible for delivering the physical design of blocks/tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation chips in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 5-7 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Requirements Bachelor or master Degree with 3-10 years of Analog Layout experience. Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable: Mixed signal/analog/high speed layout, e. g. PLL, IO, RF, PMIC, OSC, DC-DC convertor, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc). Experiences in advanced technology node under 16nm/14nm/7nm. 5nm/3nm will be an added advantage. Must have expertise on Totem EMIR & Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc. ). Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc. ). Experience in top-level floorplan, hierarchical layout methodologies Programming skills in SKILL automation and circuit Design background is a plus. Good communication skills and willingness to work with global team. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment Work Experience Must have expertise on Totem EMIR & Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc. ). Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc. ). Experience in top-level floorplan, hierarchical layout methodologies Programming skills in SKILL automation and circuit Design background is a plus.