812 Physical Verification Jobs - Page 4

About The Role Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : SAP FI S/4HANA Accounting Good to have skills : SAP FI S/4HANA Central Finance Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various teams to ensure that application requirements are met, overseeing the development process, and providing guidance to team mem...

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times I...

As a Layout Design Engineer at Micron Technology's HBM Team in Hyderabad, India, your role will involve working on intensive applications such as artificial intelligence and high-performance computing solutions, specifically High Bandwidth Memory. You will collaborate with peer teams across Micron's global footprint, in a multiple projects-based environment. - Responsible for designing and developing critical analog, mixed-signal, custom digital blocks, and providing full chip level integration support. - Highly motivated with a passion for detail-oriented, systematic, and methodical approach in IC layout design. - Perform layout verification tasks like LVS/DRC/Antenna, quality checks, and d...

In a fast-paced leading-edge design environment with endless possibilities of innovation and learning, you will be responsible for ensuring flawless execution in specific areas of SoC level Physical Design such as Physical Verification, Tapeout, ESD Verification, and Pre-emptive Quality audits of incoming designs. This is a great opportunity to join a team of talented individuals working on state-of-the-art complex SoC Designs as part of Intel Foundry Design Services and Reference Design Development teams. - Integration and generation of layout and netlist views of different levels of hierarchy up to SoC. - Layout verification and signoff for IP blocks, APR partition, and SoC levels of hiera...

Job Overview In Arm's Solutions Engineering group, our primary focus extends beyond advanced System-on-Chip (SoC) development As Physical Design (PNR) Engineers, we play a critical role in shaping the future landscape of chip implementation methodologies Our expertise lies in optimizing physical designs through advanced placement and routing techniques, ensuring optimal power efficiency, enhanced performance, and improved area utilization We actively refine PNR methodologies, influence Electronic Design Automation (EDA) tools, and build comprehensive knowledge bases essential for custom SoC and CPU designs Collaborating closely across Arm's organizational divisions, we drive innovative and r...

Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and preferably hands on experience on SoC STA, Power, Physic...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis (CTS), formal verification, physical verification (DRC/LVS), power delivery network (PDN), timing closure, and power optimization. Your role will involve making PPA trade-off decisions for critical cores, ensuring timing convergence of high-frequency data-path intensive cores, and implementing advanced STA concepts. You will work on block-level PnR convergence using tools like Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. Additio...

Role Overview: As a member of the team, you will be part of a group dedicated to pushing boundaries and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will play a key role in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration for products loved by millions worldwide. Key Responsibilities: - Develop all aspects of RTL2GDS for ASIC/Mixed signal chips. - Take complete ownership of physical design integration and CAD flow for Mixed signal chip development. - Drive the closure of timing and power/Physical convergence of the design. - Contribute to physical design methodologies and automation ...

Maintain accurate records of incoming and outgoing of materials Ensure all goods are properly received with supporting documents (GRN, DC, invoice). Monitor inventory levels to prevent stockouts or overstocking of items. Plan and execute periodic physical verification and stock reconciliation. Enter and monitor all store transactions (receipts, issues, returns, transfers) in ERP. Generate daily/weekly stock, consumption, and variance reports. Maintain proper storage of materials as per category (GI sheets, copper pipes, insulation, fasteners, etc.). Follow FIFO/FEFO principles for issuance. Coordinate with Production, Purchase, and Project teams for material planning and timely supply.

. To calculate quantities for the various works as per WO pay items and as per IFC drawings. To compare the derived quantities of drawings with the certified bill validated by EIC Checking verification of monthly contractor bills as per billing cycle. Reading drawings, identifying item of works taking off quantities verification of bar bending schedule Recording of measurements at sites of concealed items, different items of works for computerized billing, bill checking and quantity verification. To check the billed quantities with respect to standard mode of measurement To check and verify Joint measurements sheet as per the standard format with detailed back-up of quantities claimed. Verif...

Role Overview: Job Title : PNR Lead Experience : 8+ Years Work location : Bangalore Job Description: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the de...

Job Description: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Your role will require collaboration with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities: - Demonstrating good knowledge of CMOS technology and physical design concepts such as flooplanning, place and route, clock tree synthesis (CTS), physical verification, and static timing analysis (STA). - Taking responsibility for developing CAD tool/flow solutions w...

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and Twitter (X). Person should have complete end-end knowledge of the Netlist- Gds Tapeout methodo...

Role Overview: As a Virtuoso Layout Engineer at Cadence, your main responsibility will be to engage with customers and prospects, assess and validate opportunities, define feasible evaluation criteria, convert prospects into business deals, and support customers in implementing the tool for their production needs. Your expertise in understanding customer workflows and analytical capabilities will play a vital role in addressing issues that impact production timelines. Having hands-on knowledge of Advance Node layout and design rules will be advantageous for this role. Key Responsibilities: - Communicate with customers to resolve issues and identify possibilities to showcase Cadence technolog...

Key Responsibilities: Perform physical verification at the SoC, core, and block levels, including DRC, LVS, ERC, ESD, DFM, and tapeout tasks. Address complex physical design challenges related to sign-off and ensure timely resolution. Maintain deep understanding of physical verification workflows and methodologies across RTL to GDS2. Collaborate with Place-and-Route (PNR) teams to support verification sign-offs at various stages. Troubleshoot and resolve LVS issues, particularly for complex analog-mixed signal IP integrations. Support verification of full-chip components including I/O rings, corner cells, seal rings, RDL routing, and bumps. Contribute to the development of sign-off methodolo...

Responsibilities: Work as part of the Design Enablement team, closely collaborating with SoC cross-functional teams Define and develop PDN and PV flows and methodologies for low geometry nodes (3nm, 5nm, 16nm) Manage requirements and define tools and flows needed for SoC-level implementation Collaborate with EDA vendors to evaluate and benchmark latest PDN & PV tools and methodologies Lead deployment and adoption of new tools, flows, and methodologies across the organization Act as a change agent in introducing innovative flow improvements and process standardization

As a Senior Layout Engineer at SILCOSYS Solutions, you will play a crucial role in designing and verifying analog circuit layouts. You will collaborate with circuit design teams, perform physical verification, and ensure compliance with industry standards. Your day-to-day tasks will involve layout design of analog circuits, circuit design collaborations, conducting design reviews, and resolving layout-related issues. Key Responsibilities - Design and verify analog circuit layouts - Collaborate with circuit design teams - Perform physical verification tasks - Ensure compliance with industry standards - Conduct design reviews - Resolve layout-related issues Qualifications - Experience in Layou...

As a Physical Design Engineer, you will be responsible for the physical design of ASICs. This includes tasks such as floorplanning, clock tree synthesis, placement, routing, timing closure, and physical verification. Your contributions will be crucial to the successful tape out cycles of multiple chips, ensuring the efficiency of the PD life cycle and ECO life cycle. Your expertise in clock-tree synthesis and power-aware PD flows, such as ADM, P&R, will be essential for the project's success. Additionally, your familiarity with PD-STA, timing constraints, and multi-mode, multi-corner timing closure will play a key role in achieving project milestones. **Qualifications Required:** - 3+ years ...

Role Overview: As a Store Assistant/Keeper at our office located in Rabale, Navi Mumbai, your primary responsibility will be to stock materials received from vendors properly to ensure easy access, identification, verification, and handling. You will play a crucial role in maintaining the stock by using appropriate methods of care and preservation to prevent damage and loss. Periodical physical verification of stock, smooth issuance of materials to internal departments, and accurate accounting of received and issued materials are key aspects of your role. It is essential to maintain receipts, records, and withdrawals of stock, provide necessary documents with outward materials, and ensure th...

Job Description Main Tasks Physical verification of Gold Packets, Cash including Vault Cash and Foreign Currency as to its correctness with the system records. Checking of ornaments as to its quantity, weight, quality and purity taken for pledge during the current gold inspection period. Checking of greater than 5 months gold packets as to its quantity, weight, quality and purity for which gold inspections were done earlier. Verification of Gold Loan pledge/release documents and reporting of anomalies if any observed. Verifying whether the ornaments pledged under all schemes are solid ornaments and LP/SP ornaments are not accepted for pledge under any schemes. Verification and reporting of a...

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shi...

Introduction: This position is for IO Design Engineer who will own End-to-End development of IO IPs. The successful candidate needs to have an exceptional background in CMOS design, End-to-end Analog/IO IP development experience, and needs to be a team player with a solution-oriented approach. Essential Responsibilities: Responsible for the development and delivery of IO IPs (GPIO, LVDS, SSTL, HSTL, MIPI, etc) in multiple technology nodes and achieving corresponding PPA indicators Responsible for collaborating to defining IO IP architecture design and circuit design, simulation verification and reliability assurance Collaborate in the design and implementation of test chips, packaging design...

Roles and Responsibilities Manage daily store operations, including inventory control, material receipt, and stock taking. Ensure accurate GRN (Goods Received Note) and MRN (Material Reject Note) processing for all materials received or rejected. Conduct physical verification of stored items to maintain accuracy in inventory records. Implement FIFO (First-In-First-Out) method for storing and issuing materials. Perform regular stores maintenance tasks such as cleanliness, organization, and upkeep of the storage area.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC PD ENGINEER) The Role The position will involve w...

Role: PD Lead Experience: 7+yrs Location: Bangalore Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, ph...