1022 Physical Verification Jobs - Page 4

General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, El...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning(for hierarchical designs),placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations. Should have worked on 45nm, 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Interface with front-end ASIC teams to resolve issues. Excellent communication...

Job Overview: Physical Design Engineer implements the entire ASIC/SoC back end design flow from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next generation state of the art process technologies. Physical Design Engineer Experience: 5 Years & above (Mandatory). Education: BE/ ME/B. Tech/M. Tech/MS or equivalent disciplines with an emphasis on VLSI design Location: Bengaluru, India EMPLOYMENT TYPE: FULL TIME Roles & Responsibilities: - Take complete ownership of the implementation of Block level designs and Chip level design - Responsible for planning and execution of all aspects of Physical Design includin...

As an experienced Physical Design Engineer at Tessolve in Bangalore, your role will involve the end-to-end physical design flow from RTL to GDSII at advanced technology nodes such as 7nm, 5nm, or below. Your responsibilities will include optimizing chip area, power, and performance through floorplanning and partitioning, as well as optimizing standard cell placement, buffer insertion, and clock tree synthesis during placement and CTS. You will work on congestion analysis, RC extraction, static timing analysis (STA), power optimization techniques, physical verification, and sign-off analysis. Collaboration with RTL design, DFT, and verification teams for design convergence will also be a key ...

- Perform regular and physical inventory counts to compare with system records, checking for accuracy in quantity, labeling, and storage. - Prepare comprehensive audit reports with findings, track adjustments, and present information to management. Required Candidate profile - B.Com. / M.Com. with 2 years of experience in Stock Auditing. - Must be comfortable travelling across India for conducting audit. - Excellent communication skills.

- Perform physical and technical audits of mechanical systems, equipment, and structures to ensure they meet design specifications and quality standards. - Verify the construction and installation of mechanical components. Required Candidate profile - B.E. / B.Tech. Mechanical with 2+ years of experience in a mechanical engineering and auditing. - Must be comfortable travelling across India for conducting audits.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements Minimum Qualifications: Bachelor's degree in Computer Sci...

Role & responsibilities Physical Verification: Conduct timely and unannounced visits to the applicants residence and business/office address as per the loan application. Address Authentication: Verify the existence, tenure, and nature of the location. Capture geo-tagged photos/videos as per company policy. Personal Discussion (PD): Conduct in-depth discussions to assess intent, financial awareness, and information consistency. Neighbourhood Check: Gather unbiased feedback from neighbours or local shops to verify reputation, character, and actual business activity. Document Check: Physically verify originality/authenticity of documents such as utility bills, tax receipts, business licenses, e...

We are looking for a highly skilled and experienced individual for SoC PD lead position for driving SoC implementation efforts from RTL to GDSII. This role is pivotal within our talented team of engineers, ensuring that we meet our GDS release timelines, PPA requirements, and all sign-off criteria for our complex semiconductor designs. This role demands a profound technical understanding of the entire implementation cycle, from start to finish, as well as exceptional leadership skills. The successful candidate will work with various functional teams and must possess a strategic vision to drive continuous improvement in our methodologies and processes. Key Responsibilities: To be responsible ...

Job Description: Bill checking and bill booking of suppliers / contractors Payment to vendors Financial accounting in SAP (FICO / equivalent another ERP package) Bank reconciliation Preparing CMA data, loan applications to Banks, etc. Opening of local and foreign letters of credit, foreign remittances and purchase of foreign currencies Taxation of charitable trust Capitalization of CWIP on project completion, maintaining fixed assets records, physical verification of fixed assets and reconciliation with fixed asset records Core team function in SAP FICO module like company, cost canter, profit center creation, master creation, budget upload / revision, account opening etc. Any other responsi...

As a Digital Physical Design Engineer, you will play a crucial role in the physical implementation of complex digital integrated circuits. Your responsibilities will include: - Execute physical design activities such as floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). - Perform physical verification (DRC, LVS, Antenna) and address related issues efficiently. - Conduct power integrity analysis focusing on IR drop and EM, and optimize designs for enhanced power efficiency. - Participate in design-for-test (DFT) implementation and ensure the verification of test structures. - Collaborate closely with design, verification, and DFT teams to e...

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for p...

Hope you are doing well. We are currently hiring for an STA Engineer position at Eximietas Design , and based on your background, you may be an excellent fit for this role. Please find the detailed Job Description below. Job Description STA Engineer (Static Timing Analysis) Company: Eximietas Design Location: Bangalore Experience: 6+ Years About the Role: We are seeking an exceptional STA Engineer to join our semiconductor design team. You will collaborate with talented engineers to deliver high-performance, energy-efficient, and scalable ASIC designs. This role involves leading STA efforts for complex, high-speed, advanced-node ASICs in a fast-paced environment. Responsibilities: Lead a tea...

Manage and lead a team of physical design engineers. Job also entails significant amount of hands-on work, in particular place-and-route, static timing analysis, formal verification, physical verification, and power analysis. Drive implementation of physical design methodologies as required through the development of automation scripts. Work with front-end engineers to resolve timing and power issues. Evaluate new tools, and creatively drive power reduction of designs. Must be proficient and highly capable in floorplanning and time budgeting. Desired Skills & Experience: Experience level 10 to 15 years. Must possess 10+ years of hands on experience in handling block/chip level implementation...

Required skills: Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Experience 5 to 12 Years Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning(for hierarchical designs),placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations. Should have worked on 45nm, 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Interface with front-end ASIC teams to resolve issues. Excellent communication...

We are seeking a highly experienced Senior Physical Design Engineer with 8+ years of experience in block-level and full-chip physical implementation. The candidate should be proficient in physical design flows and methodologies for advanced technology nodes. Key Responsibilities: Drive physical implementation from RTL to GDSII (floorplanning, placement, CTS, routing) Perform timing analysis, congestion analysis, and physical verification (DRC/LVS) Optimize for performance, power, and area (PPA) Collaborate closely with RTL, STA, DFT, and package teams Own signoff checks (IR drop, EM, Antenna, Crosstalk, etc.) Support tape-out and silicon validation activities Requirements: 8+ years of experi...

We are looking for a skilled SAP DRC Consultant with 19 years of experience to join our team at Forward Eye Technologies. The ideal candidate will have a strong background in SAP DRC and be able to work effectively in a fast-paced environment. Roles and Responsibility Collaborate with cross-functional teams to design and implement SAP DRC solutions. Provide technical expertise and support for SAP DRC projects. Develop and maintain documentation for SAP DRC implementations. Troubleshoot and resolve complex technical issues related to SAP DRC. Conduct training sessions for end-users on SAP DRC functionality. Work closely with stakeholders to understand business requirements and develop solutio...

As a Physical Design Engineer with Innovus skills, your role will involve the following key responsibilities: - Solid experience in place & route flow, including placement guidelines, clock-tree synthesis, routing, and timing optimizations. - Experience with hierarchical designs and/or Low Power implementation is considered an advantage. - Proficiency in Synthesis, interfacing with RTL, and implementation. - Expertise in Floorplan design, which includes placement of hard macros and congestion reduction techniques. - Familiarity with Static Timing Analysis activities, parasitic extractions, and sign-off requirements. - Knowledge of Physical Verification processes such as DRC/LVS/DFM and chip ...

You will be part of a team responsible for creating Design Methodology solutions for various Technology nodes, focusing on developing Digital design enablement collateral to assist GLOBALFOUNDRIES customers in adopting advanced silicon technologies (12/14/22/28/40/55). Your specific responsibilities include: - RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing, and Physical Verification - Collaborating closely with EDA vendors and PDK to define, implement, customize, and qualify digital design flows - Using TCL, Python, Pandas, and Google APIs for automation in flow regressions, error/warning collection, and key design metrics comparison to ensure high...

Role & responsibilities * Candidate should be having a Bachelors degree in electrical engineering with minimum 5+ years of experience in Physical Verification * Hands on debugging skills in different physical verification checks like LVS,DRC,ERC,PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools. * Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. * Working experience in cutting edge technologies such as 5nm, 7nm and 16ff process nodes is desire Location-Bangalore

Were Hiring: Physical Design Engineer Location: Bangalore, India Experience: 5+ Years Key Responsibilities: Create IO Ring and RDL routing Perform Clock Tree Synthesis (CTS) using Cadence Innovus Conduct EMIR analysis with Ansys Redhawk Execute Physical Verification using Calibre Requirements: Strong understanding of physical design flow & methodologies Excellent problem-solving and debugging skills Ability to thrive in a fast-paced, collaborative environment Apply Now: Send your resume to surapandey@allegisglobalsolutions.com

Hiring VLSI Engineers with 3-12 yrs experience in RTL Design/Verification, STA, DFT, PD, or Analog/Mixed-Signal. Strong Verilog/SV, Spice, Python/TCL scripting, and EDA tool expertise required. Immediate joiners preferred. Multiple openings

As a Store Executive, your primary responsibility is to ensure seamless store operations by handling materials accurately, managing deliveries timely, and optimizing resource usage. Your key responsibilities include: - **Policies, Processes & Procedures** - Carry out day-to-day activities in adherence to relevant policies, processes, and standard operating procedures. - Follow established Standard Operating Procedures (SOPs) for inventory and warehouse management. - Stay updated on leading practices and trends to contribute to continuous improvement of systems and procedures. - **Store/ Inventory Management & Operations** - Receive materials meticulously and verify incoming receipts against ...