1027 Physical Verification Jobs - Page 16

Responsible for leading Physical Design and Timing Closure of low power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design , floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design, methodology and process aspects. Enable next generation of place and route engineers via mentoring and thought leadership. Your Profile You are best equipped for this task if you have: Hands-on experience in physica...

As a Physical Verification Engineer for SOC/blocks, your role involves performing physical verification for SOCs, cores, and blocks, which includes tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. You will be responsible for addressing critical design and execution challenges related to physical verification and sign-off. It is essential for you to have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Collaboration with PNR engineers to achieve sign-off at various stages of the design process is also a key aspect of your role. Your qualifications and skills should include proficiency in physical verification for SoC/full-chip and b...

Physical Design and Timing closure of Infineon SoCs targeted for IoT and MCU markets. Job Description In your new role you will: This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Candidate will be responsible to drive die area, performance, power goals for hierarchical blocks/Top. Candidate will work on various stages of physical design implementation which includes floorplanning, IO planning, packager co-design, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IRdrop, physical verification checks. Candidate is expected to have deep understanding and hands-on experience in implementing ...

We are looking for a skilled professional with 5-15 years of experience to join our team as an SCOM in IDESLABS PRIVATE LIMITED, located in [location to be specified]. The ideal candidate will have a strong background in recruitment services and excellent communication skills. Roles and Responsibility Manage and coordinate recruitment activities to meet client requirements. Develop and implement effective recruitment strategies to attract top talent. Build and maintain relationships with clients and candidates for successful placements. Conduct interviews and assessments to identify the best candidates. Collaborate with internal teams to ensure seamless recruitment processes. Analyze recruit...

We are looking for a skilled SAP DRC Engineer with 7 to 12 years of experience. The ideal candidate will have expertise in the SAP DRC module and BTP of SAP, SD, FI, E-Doc Cockpit, and project management skills. This position is available in PAN India, including Bangalore, Hyderabad, Chennai, Noida, Pune, and Gurgaon. Roles and Responsibility Design and implement SAP DRC solutions to meet business requirements. Collaborate with cross-functional teams to ensure seamless integration of SAP DRC with other modules. Develop and maintain documentation for SAP DRC projects. Provide training and support to end-users on SAP DRC functionality. Troubleshoot and resolve technical issues related to SAP D...

We are looking for a skilled professional with 05-20 years of experience to join our team as a (VLSI) Physical Design (PD) expert in Bangalore, Hyderabad, Kochin, and Pune. The ideal candidate will have hands-on experience with Netlist2GDSII Implementation, including floor planning, placement, CTS, routing, STA, power integrity analysis, physical verification, and programming in Tcl/Tk/Perl. Roles and Responsibility Implement Netlist2GDSII for various projects. Perform floor planning, placement, CTS, routing, STA, and power integrity analysis. Conduct physical verification and ensure successful project delivery. Collaborate with cross-functional teams to meet project goals. Develop and maint...

We are looking for a skilled professional with 7 to 15 years of experience in the field of Physical Design to join our team. The ideal candidate will have a strong background in Floor Planning, Innovus, Fusion Compiler, and programming skills in Tcl/Tk/Perl. Roles and Responsibility Develop and implement physical design methodologies for submicron technology nodes. Utilize expertise in Floor Planning, Innovus, and Fusion Compiler to optimize design performance. Collaborate with cross-functional teams to ensure seamless integration of physical design with other components. Apply knowledge of physical design principles and methodologies to improve design quality. Troubleshoot and debug complex...

Job Description: Bachelor s Degree in Electrical/Electronic Engineering or equivalent. Work experience in PDK development. Expertise in SKILL, Perl programming languages. Knowledge of deep sub-micron CMOS processes, device physics and layout design. Experience with custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors. Experience in developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting. Experience with physical verification tools for DRC, LVS and parasitic extraction, PVS, Assura is a plus. Working knowledge of revision control softw...

As a Store Executive at the company, your primary responsibility will be to ensure precise materials handling, timely deliveries, and optimal resource management to maintain seamless store operations while complying with safety and statutory regulations. **Key Responsibilities:** - Conduct day-to-day activities in adherence to relevant policies, processes, and standard operating procedures - Implement and maintain established Standard Operating Procedures (SOPs) for inventory and warehouse management - Supervise the receipt division ensuring meticulous reception of materials and validate incoming receipts - Manage the transfer of materials to storage locations, ensuring safety and security p...

Responsibilities: Collaborate with cross-functional teams on project deliverables. Optimize timing closure through innovative techniques. Perform physical verification using Synopsys tools.

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

You have a job opportunity for the Manager / Senior Role Physical Design Engineer position in Hyderabad. Your primary responsibilities will include: - Performing IP/Block level PnR activities from Netlist to GDS-II - Demonstrating good knowledge of all PnR activities such as Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Executing all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handling signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Having knowledge of high performance and low power implementation methods (preferred) - Expertise in ICC2/Fusion Compil...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Working experience in Physical Design implementation areas including Synthesis, LEC, and PnR as well as good exposure to signoff areas, particularly power, timing, and IR signoff. Job Description In your new role you will: Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Design Application Engineering (DAE) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point of contact for project teams in case of issues and will...

Responsible for high-performance microprocessor blocks RTL to GDSII implementation Perform block-level synthesis, floor-planning, placement, and routing. Close the design to meet timing, power budget, and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8-12 years of industry experience in physical design methodology. Good knowledge and hands-on experience in physical design methodology, which includes logic synthesis, placement, clock tree synthesis, and routing. Should be knowledgeable ...

You are seeking a Digital/Memory Mask Design Engineer to join a dynamic team managing complex high-speed digital memory circuit designs at NVIDIA. As a part of the team, you will be involved in reinventing the field of artificial intelligence and enhancing human creativity and intelligence. You will work in a diverse and supportive environment where delivering your best work is encouraged. Your responsibilities will include: - Executing IC layout for innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes of 3nm, 5nm, 7nm, and lower nodes using industry-standard methodologies. - Leading the architecture and layout design of critical memory subsystems, ...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. Basic Qualifications Strong academic and technical background in electrical engineering. A Bachelor's de...

Job Summary: The Store Incharge is responsible for the overall management of the store, including inventory control, material handling, record-keeping, and ensuring timely availability of materials for smooth operations. The role involves supervising staff, maintaining stock levels, and ensuring proper documentation of all inward and outward materials. Key Responsibilities: Manage and oversee daily store operations and inventory movement. Receive, inspect, and verify all incoming materials as per purchase orders and invoices. Maintain accurate stock records (inward, outward, and balance) in registers/software. Issue materials to departments/sites against approved requisitions. Ensure proper ...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. **Key Responsibilities:** - Participating in ASIC development projects with a focus on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. - Creating design experiments, conducting detailed PPA comparison analysis, collaborating with various teams for optimizati...

As a Memory Layout Engineer at our company, you will play a crucial role in designing and integrating layouts for advanced memory blocks across leading-edge process technologies. Your primary responsibilities will include: - Designing layouts for essential memory components such as Control and Digital logic, Sense amplifiers, Bit-cell arrays, and Decoders. - Working with advanced process nodes like 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, and FinFET technologies. - Developing memory compilers, addressing layout-related issues, and ensuring optimization. - Proficiency in Routing Congestion, Physical Verification in Custom Layout. - Knowledge of verification checks like DRC, LVS, ERC, Antenna, LPE, DF...

You should have at least 3+ years of relevant experience in SoC Physical design, with a focus on multiple technology nodes including 5nm for TSMC and other foundries. Your expertise should include hands-on P&R skills, particularly in ICC/Innovus. You must possess expert knowledge in all aspects of Physical Design (PD) from Synthesis to GDSII, with a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. - Experience in taping out multiple chips and working at the top level in the latest technology nodes will be highly beneficial. - Collaboration with CAD, Methodology & IP teams for PD implementation is critical, r...

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems, including circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems. Your role will involve developing cutting-edge products and collaborating with cross-functional teams to ensure that the solutions meet performance requirements and contribute to the projects" success. Key Responsibilities: - Plan, design, optimize, verify, and test electronic systems - Work on circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems - Develop cu...