401 Physical Verification Jobs - Page 16

About The Role Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities ? 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipro’s standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for ‘will’ based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation ? Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) ? Mandatory Skills: VLSI Physical Verification. Experience5-8 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

About The Role Experience in Mixed-Signal layout design, holding bachelors degree in electrical/Electronic Engineering. To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experienceTSMC 7nm, 5nm, 10nm,28nm , 45nm,40nm EDA Tools Layout EditorCadence Virtuoso L, XL Physical verification DRC, LVS, Calibre Secondary Skills IO layout

This role is based in Bangalore. But youll also get to visit other locations in India and globe, so need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is the role: Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Can you collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution! An ability to work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on groundbreaking technologies (7nm and forward). We require to develop & deploy training and technical support to customers using Siemens EDA tools. We dont need superheroes, just superminds! Experience & Qualifications: We are looking out for a candidate with ME/M.Tech in VLSI or Microelectronics with 7+ years of experience in RTL2GDSII, Physical Design with mainstream synthesis and P&R tools. We are looking for someone with hands on experience in Synthesis, DFT insertion, Logical Equivalence and Physical Design. We need hands-on experience with commercial synthesis tools such as Genus, DC, Fusion Compiler which is a must. Tapeout experience of 2 or more projects or proficient experience in implementation CAD flows and methodology. Hands on knowledge on place & route tools like Synopsys-lCC2, Cadence-Innovus or Aprisa and Logical Equivalence tools like Conformal is an advantage. Good understanding of timing, power, and area trade-offs. Knowledge on Static Timing concepts, hands on knowledge on Tempus, Primetime, knowledge on Physical Verification, DRC/LVS, IR drop analysis, hands on mPower etc is a plus. Do you have the ability to pick up new flows, learn on the job and influence QOR? Strong verbal and written communication skills; good presentation skills; good problem solving and debugging skills.

Skills Required 10-15years of relevant experience in ASIC Physical Verification Good understanding of overall design Flow from RTL to GDS. Hands on Experience on Physical Verification closure of full chip & Hierarchical Designs Hands on DRC & LVS Experience on Lower node Technologies with Synopsys/Siemens Tools Good knowledge on PnR flow Knowledge on Perl / TCL / Python scripting language Experience on multi voltage designs Good understanding of all Phases of Physical Design (PnR/STA/PV/IR) Responsibilities Responsible for Block/ Chip Tile PV closure to achieve the best PPA DRC & LVS closure for Block and Full Chip for complex hierarchical Designs in 5nm/3nm nodes Interaction with IR, IP , ESD & PD teams for Physical Verification Convergence & Resolving Conflicts Able to work on multiple blocks at same time with minimal supervision Responsible for Full Chip LVS & DRC closure Responsible for Analog integration closure for all IP"s used in SOC Interactions with Foundry team for Full chip Tapeout

Job Description Physical verification and readiness of equipment and instrument for process. Arranging the process accessories and consumables in process area before batch execution. Coordination for dispensing of raw material required for the production processes. Preparation of process, equipment and area related SOPs and EOP s. Preparation of process, area and equipment qualification/ validation protocols. Preparation and execution of various reports like process, equipment, area qualification and validation. Request and Issuance of BPR. Preparation and review of BPR. Preparation and execution of study protocols, URS as and when required Work Experience Four to Seven Years Education Masters in Biotechnology or Biochemistry B.Tech in Biotechnology or Biochemistry Competencies

Role & responsibilities Responsible for Despatch of Finished Goods Responsible for Scanning the product details and execution of Indents Responsible for maintaining Finished Goods stock Preferred candidate profile Any Graduate with knowledge of computer skills

To provide Trade related Services to Customers and to meet turnaround times as per the Service Level Agreement & productivity standards Responsible for monitoring operational & customer service-related activities of the CPC. Monitoring, timely reporting to Manager, and taking corrective action of irregular items to facilitate early resolution. Comply with internal operating procedures & Key Control Standards To ensure speedy resolution of customer queries & complaints, in accordance with laid down procedures & Quality standards. Perform relief function for Officer, Customer Service / Assistant Manager as per requirements. Assist Managers/ Assistant Managers in monitoring all transactions to ensure obligations/payments duly met. Ensure compliance of all policies and procedures issued in relation to money laundering prevention. Ensure strict compliance of Group Sanctions Procedures. Ensure strict implementation of Group Policies on KYC, Group Code of Conduct Ensure timely archival of documents and ensure maintenance of records as per the Group policy. Ensure no operating losses. Escalate issues on timely basis to Unit Managers. Key Responsibilities Service delivery according to set standards. Compliance of statutes, internal operational procedures/Group guidelines & Regulatory requirements. Risk assessment & control Staff management/training/morale Preparation of PPCL and Scanning activities. Receiving documents, Registration in IMEX and despatching documents Handling of Delivery and support. TRAACS/ IDPMS/EDPMS Support to Import Team. Updating of A1 and GR/Shipping Bills and compiling R Returns in RBI FETERS R Returns package. Physical verification of bills Preparation of internal/external Returns, Reports and MIS statements Handling customer calls and queries General filing / Archival of record. Maintenance of SLA by handling daily work activities as directed by Manager Improvement of overall productivity of the unit by Assisting Officers/Asst Managers in their daily activities To act in complete compliance with the Bank s Data confidentiality policy at all times which also governs sending of data to external parties over email. To assist Unit Head, Trade services in completion of any projects as assigned from time to time. Responsible for the health and safety aspects at the workplace. Take reasonable care for the health and safety of co-workers and those who may be affected by own actions or omissions. Co-operate with Management to support and promote Health and safety in the workplace. Ensure that team members are adequately trained and supervised to perform their tasks in a safe manner. Ensure that own actions do not put others at risk. Work in a healthy and safe manner. Encourage others to work in a healthy and safe manner. Report all accidents and incidents and Bring to the attention of the management any hazard in the workplace. Key stakeholders Customer / SCB Staff / GBS Skills and Experience Product Experience LAP, BIL, PL and LAS Distribution Relationship Management Digital Knowledge Customer Management Strong Communication Skills Effective People Skills Qualifications Reasonably good communication skills Knowledge of MS Office Overview of Master directives / Trade Products Together we: Do the right thing and are assertive, challenge one another, and live with integrity, while putting the client at the heart of what we do Never settle, continuously striving to improve and innovate, keeping things simple and learning from doing well, and not so well Are better together, we can be ourselves, be inclusive, see more good in others, and work collectively to build for the long term In line with our Fair Pay Charter, we offer a competitive salary and benefits to support your mental, physical, financial and social wellbeing. Core bank funding for retirement savings, medical and life insurance, with flexible and voluntary benefits available in some locations. Time-off including annual leave, parental/maternity (20 weeks), sabbatical (12 months maximum) and volunteering leave (3 days), along with minimum global standards for annual and public holiday, which is combined to 30 days minimum. Flexible working options based around home and office locations, with flexible working patterns. Proactive wellbeing support through Unmind, a market-leading digital wellbeing platform, development courses for resilience and other human skills, global Employee Assistance Programme, sick leave, mental health first-aiders and all sorts of self-help toolkits A continuous learning culture to support your growth, with opportunities to reskill and upskill and access to physical, virtual and digital learning. Being part of an inclusive and values driven organisation, one that embraces and celebrates our unique diversity, across our teams, business functions and geographies - everyone feels respected and can realise their full potential.

What You'll Be Doing : - In this position, you will expect to lead all block/chip level PD activities. - PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. - Work in collaboration with design team for addressing design challenges. - Help team members in debugging tool/design related issues. - Constantly look for improvement in RTL2GDS flow to improve PPA. - Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. - Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications : - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. What We Need To See : - Strong experience in Physical Design. - Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. - Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Well versed with timing constraints, STA and timing closure. - Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. - Ability to multi-task and flexibility to work in global environment. - Good communication skills and strong motivation, Strong analytical & Problem solving skills. - Proficiency using Perl, Tcl, Make scripting is preferred. - Widely considered to be one of the technology worlds most desirable employers, offers highly competitive salaries and a comprehensive benefits package. Require candidates with a minimum of 5 years of relevant experience

Physical Verification of Stock,day to day stores,purchase work of materials incoming outgoing,ledger updating computerized,reconcile.Daily stock checking, Monthly receipt, Prepare GRN against Purchase order.Submit monthly stock statement.follow up. Required Candidate profile Study Analysis of wastage and consumption pattern of the material and give the feedback to the concerned HOD.Yearly work stock valuation, Inventory control, record keeping.Monthly reconciliation

Conduct physical verification and tagging of inventory and fixed assets, ensure data accuracy, reconcile records, identify discrepancies, support audit processes, and assist in maintaining updated asset registers for compliance and reporting.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 12+ years Hardware Engineering experience or related work experience. 12+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

As our ideal candidate, you are a seasoned professional with a deep understanding of CMOS analog and mixed-signal Layout Design Engineering. You thrive in a collaborative environment and are passionate about pushing the boundaries of technology. With over 5 years of experience, you have honed your skills in designing complex PLLs, VCOs, charge pumps, and high-speed digital circuits Layout. You are detail-oriented, capable of coordinating with various teams, and have a proven track record of delivering high-quality designs. Your strong foundation in electrical engineering, combined with your innovative mindset, allows you to tackle diverse problems creatively and effectively. With excellent communication skills, you can articulate complex technical concepts to both technical and non-technical stakeholders, ensuring seamless collaboration and project success. What You ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits in PLL and other IP Create and optimize layout designs using industry-standard EDA tools. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Define, design and develop complex RF clock path Participate in design reviews and provide feedback to improve design quality. Work closely with circuit designers to understand design specifications and constraints. Contribute to the development and enhancement of layout design methodologies and best practices. Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: Ensure the highest quality and performance of our analog and mixed-signal integrated circuits. Drive innovation by developing cutting-edge layout designs that push the boundaries of technology. Enhance the manufacturability and reliability of our products through meticulous design and verification processes. Contribute to the overall success of our projects by providing valuable feedback during design reviews. Improve design methodologies and best practices, fostering a culture of continuous improvement. Support the growth and development of junior engineers by sharing your expertise and knowledge. What You ll Need: Bachelors or Masters degree in Electrical Engineering or a related field. 7+ years of experience in A&MS layout design for integrated circuits. Hands physical design experience of passive elements used in PLL RC filter, LC oscillator Basic knowledge of PLL operating blocks Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented env Who You Are: Innovative thinker with a passion for technology and problem-solving. Excellent communicator, capable of articulating complex concepts clearly. Detail-oriented with a strong focus on quality and precision. Collaborative team player who thrives in a dynamic work environment. Adaptable and able to manage multiple priorities effectively

Working on producing highly optimized hardware IP for the ARC family of configurable processors. Collaborating with an international multi-disciplinary team on the qualification, benchmarking, and test chip implementation of new microprocessor IPs. Participating in in-house test chip designs and development platforms to learn about potential applications of our microprocessor IPs. Assisting in customer sales and design-ins of our IP, providing technical support and expertise. Implementing a comprehensive implementation flow that is configurable and supported by Synopsys memory compilers and standard cell libraries. Ensuring the highest standards of quality in physical verification and IR processes. The Impact You Will Have: Contributing to the development of cutting-edge microprocessor IPs that set industry standards. Enhancing the capabilities of our customers by enabling them to develop highly sophisticated embedded designs. Driving the success of our products through your expertise in physical verification and IR. Supporting our sales team by providing technical insights and facilitating design-ins. Improving the efficiency and configurability of our implementation flows. Helping to position Synopsys as a leader in the semiconductor industry through continuous innovation. What You ll Need: Bachelor s degree in electronics engineering or computer science; Master s degree is a plus. Minimum of 5 years of related experience in physical verification and IR. Proficiency in Verilog/VHDL. Expertise in Unix, Perl, and TCL scripting. Understanding of microprocessor design is highly desirable. Who You Are: A detail-oriented professional with strong analytical skills. An excellent communicator with the ability to convey complex technical concepts effectively. A team player who thrives in a collaborative, international environment. A proactive learner who stays updated with the latest industry trends and technologies. A problem solver who enjoys tackling challenging technical issues

Develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. Work with leading edge designs and teams to drive the industry best PPA for IP designs. Evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO s. Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. Work as a liaison between EDAG tool and IP design teams. Continuously improve and refine design processes to enhance efficiency and performance. The Impact You Will Have: Drive innovation in high-speed digital IP core and Subsystem development. Enhance the efficiency and effectiveness of our design and verification processes. Contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. Ensure the highest quality standards in the design and implementation of our products. Facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. Support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements. What You ll Need: BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. Direct hands-on experience with Primetime, Primepower/PTPX, or industry equivalent tools. Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. Good analysis, debugging, and problem-solving skills. Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings. Familiarity with other Synopsys tools such as StarRC, ICV, and experience with Ansys RedHawk is a plus. Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus

Building quality setup environments based on technology data from worldwide foundries. Writing scripts to automate processes and perform quality assurance on the environment. Working with EDA tools, including simulators and verification tools. Collaborating with local and international experts to find solutions to complex problems. Working independently while building productive working relationships with cross-functional teams. Continuously learning and exploring new technologies to enhance your skills and knowledge. The Impact You Will Have: Contributing to the creation of high-quality setup environments that enable efficient technology development. Automating processes to improve efficiency and accuracy in the engineering workflow. Enhancing the functionality and reliability of EDA tools through rigorous testing and verification. Solving complex problems by leveraging expertise from diverse, global teams. Fostering a collaborative environment that promotes innovation and continuous improvement. Driving the success of Synopsys projects and initiatives with your technical skills and dedication. What You ll Need: A bachelors degree and a minimum of 2 years of related experience or an advanced degree in Electronics/Electrical Communication Engineering/Cybernetics or a similar field. Proficiency in at least one programming language such as Python, Tcl, or Perl. An exceptional desire to learn and explore new technologies. Good investigation and problem-solving skills. Familiarity with physical verification flows like LVS/DRC/FILL/DFM and an understanding of layout design rules. Prior experience in Analog design is a plus. Knowledge and experience in tool/runset development/support is a plus. Experience in a UNIX/Linux environment. Strong communication skills and the ability to build productive internal and external working relationships. Who You Are: A collaborative team player who thrives in a diverse and multicultural environment. An independent worker who can manage tasks with minimal supervision. An effective communicator who can convey technical information clearly and concisely. An innovative thinker who is always looking for ways to improve processes and solve problems. A dedicated professional with a passion for technology and a commitment to continuous learning

* Collaborate with cross-function al teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits. * Create and optimize layout designs using industry-stand ard EDA tools. * Perform physical verification and design rule checks to ensure design integrity and manufacturabil ity. * Participate in design reviews and provide feedback to improve design quality. * Work closely with circuit designers to understand design specifications and constraints. * Contribute to the development and enhancement of layout design methodologies and best practices. * Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: * Ensure the delivery of high-quality layout designs for PVT Sensor IP development, integral to SOC subsystems. * Enhance the manufacturabil ity and reliability of our silicon lifecycle monitoring solutions. * Drive innovation in layout design methodologies and best practices. * Collaborate effectively with circuit designers to meet design specifications and constraints. * Contribute to the overall success of the rapidly expanding PVT IP group. * Support Synopsys leadership in the market for process, voltage, temperature, current, and droop sensors. What You ll Need: * Bachelor s or master s degree in electrical engineering or a related field. * 5+ years of experience in A&MS layout design for integrated circuits. * Proficiency in industry-stand ard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. * Exceptional knowledge of layout design methods, techniques, and methodologies. * Experience with physical verification tools, such as Calibre or Assura. * Understanding of semiconductor process technologies and their impact on layout design. * Excellent problem-solvin g and systematic skills. * Ability to work effectively in a team-oriented environment. * Good communication and interpersonal skills.

We are looking for a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities. Responsibilities include complete digital implementation from RTL to GDS including Synthesis, Floor-Planning, Power Planning and Analysis, CTS, Placement and Routing, STA, Formal Verification, EMIR Signoff and physical verification. The individual will contribute both on the implementation side as well as flow development for a variety of advanced high performance interface IPs, Test chips & Subsystems at latest techno nodes. The successful candidate: - has solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design. - has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints - has good scripting & programming skills (Perl, Tcl, Python etc); knowledge of CAD automation methods. - Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements - Independent, timely decision maker and able to cope with interrupts - Knowledge of IP Subsystem implementation & FE flows are added advantages 8+ years of hands-on experience in ASIC physical implementation and EDA tools with recent contribution to project tape-outs. Must demonstrate knowledge of the Synopsys tools, flows and methodologies including Design Compiler, IC Compiler/2, Fusion Compiler, Primetime, Formality, Star-RCXT, Hercules/ICV and other industry tools.

We are seeking a highly motivated and experienced Digital Design Manager to lead a team of seasoned digital design engineers. You possess a deep understanding of the ASIC digital design flow, along with hands-on experience in HDL coding, RTL2GDSII flow, and scripting languages. You excel in managing project execution from defining specifications to silicon validation and characterization. Your leadership skills foster a collaborative environment, driving your team to meet stringent project requirements and deliver superior quality designs. With a minimum of 10 years in digital design and at least 3 years in a managerial role, you bring a wealth of knowledge and a proven track record of successful project completions. What You ll Be Doing: Work closely with 3DIO Phy Architects to define specifications and micro-architecture, supporting early evaluations and feasibility studies to meet customer and system requirements. Lead the execution of digital design solutions for 3DIO Phy projects, ensuring robust and high-performance designs. Own the implementation of RTL in Verilog and sign-off using Spyglass CDC/RDC/Lint tools. Verify the RTL to test desired functionality, coverage, and corner cases using state-of-the-art verification methods. Oversee the full execution of RTL2GDSII, including timing constraints, DFT insertion, test coverage, formal verification, physical implementation, timing closure, physical verification, EMIR, and reliability sign-off. Support silicon validation and characterization through test chip implementation. Manage team members and operations, including career development and planning. The Impact You Will Have: Drive innovation in digital design solutions for 3DIO Phy projects, enhancing Synopsys product offerings. Ensure high-quality and robust designs that meet customer requirements and improve system performance. Streamline the digital design process from specification to silicon validation, reducing time-to-market. Lead a team of talented engineers, fostering a collaborative and productive work environment. Contribute to the continuous improvement of design methodologies and best practices. Support Synopsys position as a leader in the semiconductor industry through successful project deliveries. What You ll Need: Excellent understanding of ASIC digital design flow with hands-on experience in HDL coding. Proficiency in writing synthesis constraints and basics of STA. Knowledge of Lint/CDC/RDC and RTL2GDSII flow. Working knowledge of scripting languages like Perl, Shell, Python, and Tcl. Experience in leading a small team of digital design engineers to execute projects. Knowledge of high-speed/DDR PHY Layer with lane redundancy implementation is highly desirable. Exposure to FIFO, test (ATE and characterization bench), silicon validation, and debugging. Familiarity with Synopsys toolset is highly desirable. Minimum 10 years of relevant digital design experience with at least 3 years as a people manager. B.E/B.Tech/M.Tech in ECE/EE. Who You Are: Strong leadership skills with a proven track record of managing and developing teams. Excellent problem-solving abilities and attention to detail. Effective communication skills, both written and verbal. Ability to work collaboratively in a fast-paced, dynamic environment. Innovative and proactive mindset with a passion for continuous improvement

We are seeking an experienced, initiative-taking, and high-calibre individual to join our SLM Monitors group as a Monitor IP Design, Architect. Someone who thrives in a collaborative environment and has a passion for creating innovative technology. Have a strong technical background in Custom Circuit design, System Design, methodologies and tools and is adept at working with advanced finfet / GAA process challenges. Proactive analytical person with a keen eye for detail and a dedication to delivering high-quality results. Excellent communication and people skills and can collaborate effectively with internal teams and external customers. Driven by a desire to innovate and contribute to the success of our innovative technology products. Job Descriptions Looking forward to work on conceptualizing, designing and productizing state of the art Monitor IP to be used in SLM monitors realized though ASIC design flow. Work on Architecting sensing elements for on-chip Process, Voltage, Temperature, glitch and Droop monitors for monitoring silicon biometrics. You will be the part of SLM team. Individual should have strong technical experience in full custom mixed-signal circuit design, circuit simulations, working knowledge of custom layout, and pre-post-silicon characterization. Additional responsibilities include: Development of statistical simulation methodologies. Liaising with layout team to achieve best possible design solution. End to end ownership of the designed custom cells. Deployment of new circuits into test chips and post-silicon characterization Architecting new sensors and enhancing existing ones through collaboration with other architects and stakeholders. Building and refining design flows to enhance efficiency and effectiveness. Conducting pre and post-layout simulations and characterization across various design corners. Ensuring designs meet advanced finfet / GAA reliability and aging, reliability and Automotive grade requirements Working closely with the RTL, Verification and Physical Design teams for ensuing integration and Quality. Owning the product from Spec to Silicon report. Preferred skills: Strong custom design experience - specification, circuit design description and schematics. Strong understanding of device Physics and Can work independently and debug and provide circuit solutions. Hands on experience with circuit design & simulation tools, IC design CAD packages - from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies. Job Requirements BS or MS degree in Electrical Engineering with 15+ years of relevant industry experience. Sound knowledge of custom / Standard cell design methodologies, layout tools, and physical verification. Familiarity with advanced finfet / GAA process challenges, simulation techniques and modeling.

An experienced and passionate Layout Design Sr Engineer with a strong background in Analog and Mixed Signal Circuit Layout. You possess a deep understanding of semiconductor device physics and have hands-on experience in EDA tools for custom mixed signal layout flows. Your expertise in CMOS and FINFET technologies, coupled with your knowledge of CMOS fabrication technology, equips you to handle deep sub-micron effects and their impact on layout. You are self-directed, detail-oriented, and have excellent problem-solving and communication skills. Your enthusiasm for learning and exploring new layout techniques drives you to innovate and excel in your role. What You ll Be Doing: Design and development of transistor-level analog and mixed signal layout. Creating device/block level floorplans, performing placement, routing, and physical verification. Troubleshooting physical verification issues to achieve clean and desired results. Creating and reviewing layout documents to ensure they meet quality standards and are delivered on time. Collaborating with cross-functional teams to optimize the layout design process. Staying updated with the latest industry trends and advancements in layout design techniques. The Impact You Will Have: Contributing to the development of high-performance silicon chips. Ensuring the reliability and accuracy of analog and mixed signal layouts. Enhancing the efficiency of the layout design process. Supporting the delivery of high-quality products that meet industry standards. Facilitating innovation and continuous improvement in layout design techniques. Helping Synopsys maintain its leadership position in the semiconductor industry. What You ll Need: Bachelors or masters degree in a relevant field. Minimum 3 years of experience in analog and mixed signal circuit layout. Experience with analog layout flow and EDA tools for custom mixed signal layout flows. In-depth knowledge of semiconductor device physics and analog circuits. Proficiency in CMOS and FINFET technologies and CMOS fabrication technology. Understanding of deep sub-micron effects and their impact on layout. Knowledge of EMIR, cross talk, shielding, and their impact on design. Experience in Tcl is a plus. Who You Are: Self-directed and detail-oriented. Excellent problem-solving skills. Strong communication skills. Passionate about learning and exploring new layout techniques

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

Track and manage stock levels, perform regular stock audits. Receive and store goods, ensuring proper labeling and org Process internal requisitions and dispatch items as needed Maintain accurate records of stock movements and report discrepancies Required Candidate profile 2+ years in store/warehouse operations (preferably in manufacturing) Knowledge of inventory management systems, good organizational skills Able to lift heavy items and work in a warehouse environment.

Role & responsibilities 1.Job description - Analog Layout: Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Expertise on complete PNR flow CTS,routing, Timing Closure. Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout Qualifications:- BTECH/MTECH Location: Bangalore & Noida Experience:- The Engineers with 5 to 10 years of Experience 2.Job description - Physical Verification- Exciting Opportunity for Physical Verification Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies. Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended. Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process. Address lithography and process variation concerns. Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication. Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process. Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress. Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations. Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues. Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics. Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process. Documentation: Maintain detailed documentation of verification processes, methodologies, and results. Qualifications:- BTECH/MTECH Experience:- The Engineers with 5 to 10 years of Experience Location:- Bangalore/ Noida