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Lead Engineer, STA Synthesis Vhunt4u

5.0 - 10.0 years

80 - 85 Lacs

bengaluru

Work from Office

Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metasta...

Posted 12 hours ago

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