6 Phy Jobs

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Key Responsibilities Design and develop bare metal & RTOS-based firmware/software for a 5G SoC – specifically device driver and lower PHY. Assist with the definition, development and verification of SW/FW products in accordance with company & industry standards, policies & procedures. Run & test developed SW/FW both in simulation & on actual HW in lab (lab may be remote). Collaborate closely with Applications, Systems, HW and SW/FW teams to determine SW/FW requirements. Participate in architecture & code reviews. Produce documentation e.g., design specs, developer & customer user guides, etc. Read and understand detailed technical specifications. Individual contribution is the main role, with some technical leadership and mentorship. Job Requirements 10+ years’ experience required. B.E EE/CS required, M. Tech EE/CS preferred. Strong coding skills in C, C++, Python. Experience with ARM or similar embedded SoC development environments. Experienced in RTOS principles and concepts, and hands-on experience in any RTOS. Comfortable with configuration management, version control and modern software development flows (e.g., Agile, Scrum, Lean). Excellent debug skills. Good communication, documentation & presentation skills. Demonstrate initiative to drive technical issues to resolution. Desirable Skills Prior System on a Chip (SoC) product development experience. Good understanding of cellular wireless protocols (MAC/PHY), especially 4G LTE or 5G NR. Be able to work productively and independently. Experience using GIT and Jira tools. Team player with a strong sense of urgency to meet product needs on time. Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick & parental leaves.

Position #1: Lead/Senior Design Verification Engineer - CPU / RISC-V Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | RISC-V | CPU Subsystems Role Overview: We are seeking an experienced Design Verification (DV) Engineer to join our core CPU verification team focused on RISC-V based processors and subsystems . This is a hands-on role requiring strong technical knowledge in processor architecture , microarchitecture verification , and end-to-end validation of complex SoCs. Key Responsibilities: Develop and execute test plans and environments for CPU and RISC-V based subsystems. Build UVM-based verification environments for simulation and regression. Create testbenches, assertions, checkers, and functional coverage models. Debug failures using waveform viewers, logs, and deep architectural understanding. Collaborate with architects, designers, and firmware teams across all verification phases. Required Skills: 612 years of hands-on DV experience, primarily on CPU cores or RISC-V . Strong understanding of RISC-V or ARM microarchitectures . Proficient in SystemVerilog, UVM , and scripting (Python/Perl/Tcl). Experience with cache coherency, MMUs, branch prediction, or pipeline logic is a plus. Exposure to verification tools like VCS, Questa, or Xcelium . Position #2: Lead/Senior Design Verification Engineer - High-Speed PCIe Location : Bangalore Experience : 612 Years Domain : Semiconductors | SoC | High-Speed Interfaces | PCIe Gen4/Gen5 Role Overview: We are looking for a skilled Design Verification Engineer with expertise in high-speed interface protocols , particularly PCI Express (PCIe) . The role will focus on validating complex SerDes-based subsystems and ensuring full compliance and performance coverage. Key Responsibilities: Define and implement UVM-based testbenches for PCIe-based subsystems. Verify protocol-level compliance (PCIe Gen4/Gen5/Gen6). Generate, run, and debug simulations across various protocol scenarios and stress conditions. Ensure full coverage functional, code, and assertion-based . Collaborate with silicon validation and firmware teams for end-to-end test alignment. Required Skills: 612 years of DV experience with PCIe (mandatory) and high-speed interface protocols. Strong command of UVM, SystemVerilog , and assertion-based verification. Deep understanding of PCIe layers , packet formats, credit flow, and link training. Experience with VIPs (Synopsys/Cadence/Mentor) and waveform debugging tools. Knowledge of AXI/AMBA , DDR, or USB is a strong plus. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

The successful candidate will be responsible for ensuring the efficient and safe production of high-quality products. For further information, please call [ 9845798290 / 8050011327

Designation – Automation Testing / Selenium with Java / TOSCA Eligible – Any Degree Package - 8 lakhs to 15lakhs Exp - 3 years and above(Tosca/ ,Automation Testing ) Location – Bangalore , Chennai ,Bangalore Call or Whats app SUBHA HR 7550143827

The successful candidate will be responsible for ensuring the efficient and safe production of high-quality products.

Should have 4G LTE, 5G RAN protocol development, Physical layer, MAC, PDCP, RLC, RRC Should have good programming skills , C, C++ 3GPP specifications