6 Pggrid Optimization Jobs

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop innovative solutions and meet performance requirements. Key Responsibilities: - Hands-on experience in different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. - Proficiency in high frequency design & advanced tech node implement...

As a Physical Design Engineer at our company, you will be part of a dynamic team responsible for delivering high-performance design flows for advanced SoCs in sub-10nm process technology for the mobile space. Your role will involve hands-on experience in various PnR steps such as Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. Additionally, you will be expected to: - Demonstrate expertise in high-frequency design and advanced tech node implementation - Utilize in-depth understanding of PG-Grid optimization for identifying high vs low current density paths, layer/via optimization, and...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - 8-10 years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure - ...

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible in order to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be con...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Hardware Engineer at Qualcomm, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to ensure solutions meet performance requirements. To be considered for this role, you must have a Bachelor's degree in Computer Science, Electrical/Electro...

You are a Physical Design Engineer with 2-5 years of hands-on experience in different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. You should be well versed with high frequency design & advanced tech node implementation, in-depth understanding of PG-Grid optimization, custom clock tree design, and tackling high placement density/congestion bottlenecks. Your expertise should include identifying high vs low current density paths, layer/via optimization, and Adaptive PDN experience. You must have knowledge of custom clock tree designs such as H-tree, SPINE, Multi-...