Get alerts for new jobs matching your selected skills, preferred locations, and experience range. Manage Job Alerts
2.0 - 6.0 years
0 Lacs
karnataka
On-site
The position requires 2-6 years of experience with micro architecture design and system design using Verilog, SV, or VHDL. You should also have experience in Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. Familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C is essential. You will be responsible for synthesis, timing analysis using various industry standard tools, and should have proficiency in TCL and Python scripting. The ideal candidate for this role should have a notice period of immediate availability to 1 mon...
Posted 3 months ago
Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.
We have sent an OTP to your contact. Please enter it below to verify.
Accenture
123151 Jobs | Dublin
Wipro
40198 Jobs | Bengaluru
EY
32154 Jobs | London
Accenture in India
29674 Jobs | Dublin 2
Uplers
24333 Jobs | Ahmedabad
Turing
22774 Jobs | San Francisco
IBM
19350 Jobs | Armonk
Amazon.com
18945 Jobs |
Accenture services Pvt Ltd
18931 Jobs |
Capgemini
18788 Jobs | Paris,France