458 Pcie Jobs - Page 4

Post Silicon Validation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Experience in silicon lab validation for power management ICs. Experience with validation of Mixed-signal ICs. Experience in validation test planning, test development, execution, debug and report preparation. Hands-on experience of using lab equipment such as oscilloscope, signal analyzer, signal generator, etc. familiarity of programming and scripting languages like Python, Perl Experience in automation using NI Labview is an advantage Understanding of power management ICs, architecture, specifications interpretation is required Debug skills to zero in on an issue, coordination with cross-functional teams is required Skills Experience LabVIEW, PMIC, Post Silicon Validation, System Validation, Testing Validation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

• Working experience in IP/ASIC/ SoC verification • Should have the expertise to develop block level / system level verification environments using System Verilog and UVM / OVM • Experience to develop BFMs / Checkers / monitors / Scoreboards • Should have developed block/system level verification plans and tests. Should have the capability to debug test failures to find the root cause. • Should have worked on code / functional coverage. • Experience in constrained random testing is a plus. • Experience in PCIe / Ethernet / DDR / USB / Bluetooth protocols will be PLUS • Knowledge of scripting languages like Perl, Tcl Role & responsibilities Preferred candidate profile

Software Validation of device drivers used for Communication or signal generation/measurements (Eg: SPI, UART, PWM, ADC, DMA etc. ) and safety software in an independent/RTOS environment on Automotive Microcontrollers Support Leads with WBS definition and Estimations. Envisage, implement, institutionalize and maintain the verification and validation methods and infrastructure (e. g. automation to improve quality and efficiency in terms of cost and time) Drive innovation in the for m of new advancements (test methods/tools, test automation, test infrastructure) Institutionalize software test processes compliant with Automotive standards (e. g. ISO26262, ASPICE). Ownership of re views - Test Specifications Scripts. Good knowledge of Microcontroller architecture and peripherals like CAN, LIN, SPI, PCIe, Ethernet, MEMORY etc. Experience in AUTOSAR MCAL and exposure to ISO26262. Embedded system software development or Validation using C, assembly languages. Experience in the usage of LabView, NI, FPGA, oscilloscopes, logic analysers, power benches etc. Experience in embedded system development tools such as compilers, debuggers (PLS, Lauterbach), static analysers etc. Working experience in scripting languages such as Perl, python etc. Experience in the development/maintenance of the test automation and continuous integration frameworks Good knowledge of computer architecture (16/32bit), real-time systems Working experience on multicore platforms Participate and contribute to re quirements elicitation and definition phase of the project. Develop Test Architecture, Specification and Test script for MCAL device drivers. Software Validation of device drivers (Eg: MCU, SPI, I2C, CAN, LIN, Ethernet, MEMORY, Timers, ADC, and PWM etc. ) and safety software in an independent/RTOS environment on Infineon automotive microcontrollers. Develop Test Strategy and institutionalize the methods and related templates to enable the usage of the tools and test equipment wherever re quired/possible. Envisage, implement, institutionalize and maintain the verification and validation methods and infrastructure (e. g. automation to improve quality and efficiency in terms of cost and time ) Drive innovation in the form of new advancements (test methods/tools, test automation, test infrastructure). Institutionalize software test processes compliant with Automotive standards (e. g. ISO26262, ASPICE). Ownership of reviews - Test Specifications Scripts Work Experience A minimum of 3-6 years of experience in Device Driver software testing which includes a good know how of standard software development Life Cycle Experience in AUTOSAR MCAL and exposure to ISO26262 Embedded system software development or Validation using C, assembly languages Experience in the usage of NI, FPGA, oscilloscopes, logic analysers, power benches etc Experience in Embedded System Development tools such as compilers, debuggers (PLS, Lauterbach), static analysers etc Working experience in scripting languages such as Perl, python etc Experience in the development/maintenance of the test automation and continuous integration frameworks Good knowledge of computer architecture (16/32bit), re al-time systems Working experience on multicore platforms Ability and willingness to work with multi-disciplinary teams Ability to perform tasks independently

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Description / Summary Join our elite North America hardware application engineering team, and work closely with the best AEs, PEs and RD in EDA industry. Join a top class company that has been listed in Fortune magazine and Great Place to Work as one of the Worlds Best Workplaces for the eleven years in a row! You will report directly into the North America Verification Field Applications Engineering (FAE) Team, and be co-located in India alongside our RD teams. You will be a leading product expert on advanced virtual interface solutions such as Accelerated Verification IP s and Virtual Bridges solutions for Cadence s hardware emulation and prototyping platforms. Your focus will be to work on key campaigns in North America, driving differentiated HW emulation solutions at our industry leading semiconductor and system companies and you will form a key bridge between our customers, North America AEs and RD teams. Key Responsibilities Assume technical leadership for all virtual interface solutions for Palladium and Protium and become the go-to expert for the rest of the North America field AE team . Provide in-depth technical assistance in collaboration with RD to help support advanced emulation flows to secure design wins . Champion the customer needs and work closely with RD in India to develop competitive and creative technical solutions. Requirements Strong experience in hardware emulation with knowledge of interface protocols like PCIe , AMBA and Ethernet Experience in synthesizable coding style Knowledge of fundamental SoC Architectures Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC Ability to quickly analyze emulation environments and design complexity. Strong verbal and written communication skills, with the ability to effectively bridge communication channels between external customers, NA FAE team and internal RD teams. Strong teamwork skills 8+ years industry experience We re doing work that matters. Help us solve what others can t.

Location : Company Name: Mirafra Technologies Positionskill set : PCIE Experts (Design Verification) Location: Hyderabad Experience: 6 to 12 Years Open Positions: 8 Notice Period: 0 to 40 Days Preferred Job Type: Full-Time Selection Type: All offers are client selection-based Location: Hyderabad/Bangalore Job Description: Mirafra is hiring experienced PCIE Verification Engineers for exciting opportunities with leading semiconductor clients in Hyderabad. If you're passionate about solving complex verification challenges, we want to hear from you! Key Responsibilities: In-depth understanding of verification flows and methodologies Hands-on experience with complex testbenches/models in Verilog, SystemVerilog, or SystemC Strong debug skills and a problem-solving mindset Functional and SoC-level verification, including emulation exposure Proficiency in SystemVerilog, PLI/DPI interfaces, C/C++, Perl/Shell scripting , and assembly language Experience with OVM/UVM methodologies Ability to work collaboratively in a team environment Good communication and interpersonal skills Preferred Skills: Background in x86 or ARM architecture-based SoCs Experience in SoC/IP performance verification is a plus Apply Now: If you meet the above requirements and are available within 0 to 40 days, send your resume to: [swarnamanjari@mirafra.com] or Click the apply button

THE ROLE: Exciting opportunity within the Embedded BIOS development team working on latest cutting-edge embedded CPU/APU technologies. In this role you will be responsible to design, develop, and debug BIOS for internal/external systems, platforms primarily in pre-silicon emulation/simulation environment that use AMD CPU/APU. THE PERSON: This AMD (Advanced Micro Devices) team is looking for a senior level person that can help guide the team, mentor upcoming developers, provide long range strategy, and is willing to jump in to help resolve issues quickly. You will be involved in all areas that impact the team including performance, automation, and development. The right candidate will be informed on the latest trends and become prepared to give consultative direction to senior management. KEY RESPONSIBILITIES: Responsible for BIOS and pre-OS driver development including design, documentation, unit testing and debug for pre and post silicon support. Engage with technical leads to understand BIOS/firmware scope and work on implementation to meet schedules and milestones. Work with internal and external teams to ensure highest level of quality and satisfaction throughout firmware lifecycle. Must be well-organized, technically oriented, and a self-starter with a demonstrated ability to work collaboratively and coordinate activities with geographically distributed technical teams. Desire to work and succeed on fast-paced and highly dynamic environments. BIOS/FW simulation emulation experience Pre-silicon environment Hands on debugging with emulator, simulation environment. PREFERRED EXPERIENCE: 8+ years of experience in the x86 BIOS/UEFI/coreboot development Exposure to pre-silicon BIOS development in a simulation/emulation environment Experience with x86 CPU/APU architectures and associated compilation tools Expert in C language; knowledge of x86 assembly. Experience with platform bring-up. Familiar with at least one BIOS code base (AMI, Insyde, Phoenix BIOS, coreboot, EDKII) Hands on experience with hardware debugging tools like AMD HDT, ITP, Arium, etc. Able to read and interpret hardware schematics. Knowledge of ACPI, USB, NVMe, SATA, PCIe, and other PC industry standards. Hands on experience working with Reference Boards. Strong communication skills ACADEMIC CREDENTIALS: Bachelor s or Master s in Computer Engineering, Computer Science, or a closely related field #LI-SR4 Benefits offered are described: AMD benefits at a glance .

Role Greetings from Sivaltech!! Hope you are doing great!!!! We have an exciting job opportunity for Lead Design Verification Engineer in Sivaltech for both Bangalore and Hyderabad locations. Please find below the detailed Job Description and Company Profile as well. • Working experience in IP / SoC verification • Should have the expertise to develop block level / system level verification environments using System Verilog and UVM / OVM • Experience to develop BFMs / Checkers / monitors / Scoreboards • Should have developed block/system level verification plans and tests. Should have the capability to debug test failures to find the root cause. • Should have worked on code / functional coverage. • Experience in constrained random testing is a plus. • Experience in PCIe / Ethernet / DDR / USB / Bluetooth protocols will be PLUS • Knowledge of scripting languages like Perl, Tcl Sivaltech is a product engineering company with expertise in silicon design and software development. Our head office is in Milpitas, California, U.S.A. with branches in India at Bengaluru and Hyderabad& responsibilities: Outline the day-to-day responsibilities for this role. Preferred candidate profile: Specify required role expertise, previous job experience, or relevant certifications.

Role & responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Preferred candidate profile Bachelors/ Masters degree or higher in EEE/ECE 4+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

SILICON DESIGN ENGINEER 2 (AECG ASIC - SoC verification Engineer) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 2+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench under supervision from team lead. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification will be a plus Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. #LI-SR4 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification Lead) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 8 years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. #LI-RP1 Benefits offered are described: AMD benefits at a glance .

SMTS SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification Lead) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 14+years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. #LI-RP1 Benefits offered are described: AMD benefits at a glance .

Sr. Staff Digital Engineer in Bangalore, India Sr. Staff Digital Engineer Description Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go. We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics, and video processing, combined with world class software and silicon development. Overview Synaptics is looking for a Sr. Staff Digital Engineer, WLAN MAC to join our dynamic and growing WPD organization. You will be responsible for MAC architecture / design / implementation in the Wi-Fi 6/7 for IoT market. You will provide technical expertise in the latest design methodologies. You will provide expertise in Wi-Fi domain. Your responsibility includes coordinating with multiple teams on specification for design, architecture, timing closure. This position reports to the Director, Silicon Engineering. Responsibilities & Competencies Job Duties Define WiFi MAC architecture from Standard Technically lead team on design, methodology Design optimization, enhancement to cater to the need of power and area target Guide and lead the team through digital design, RTL implementation, Lint, CDC checks, timing closure, verification and coverage closure, ECO implementation and chip productization debug Work with Systems/SW team in performance analysis and propose IP enhancements Collaborate with DV team on test plans, closure of code, and functional coverage Support post-silicon bring up activities of the products working with design, product evaluation and applications engineering team Competencies Strong Digital design and Wireless technology fundamentals Conversant with Wifi 802.11 Standard, networking protocol like L3/L4 protocol Strong fundamentals in CPU architecture, Host interfaces like (PCIe, SDIO, UART etc.), Bus interconnects specially AXI/ACE/AHB/APB. Knowledge in Lint, CDC, timing constraints, synthesis, power analysis Ability to communicate complex, interactive design concepts clearly Proactive, self-starter, able to work independently in a fast-paced environment to complete projects on time with minimal guidance Well organized with strong attention to detail; proactively ensures work is accurate Positive attitude and work ethic; unafraid to ask questions and explore new ideas Resourceful and able to solve complex problems through adaptation of existing technology and investigation of new technology with a solid understanding of product architecture Analytical and able to make informed decisions based on experience Sets clear expectations and objectives, and brings parties together to drive key initiatives Ability to work within a diverse team and mentor developing team members Excellent verbal and written communication Qualifications (Requirements) Bachelors or masters degree in computer engineering, Communication, Electrical/Electronic Engineering or related field or equivalent 12+ years of experience in IP design Proven experience in designing digital circuits for wireless product Understanding of digital IC design flow (design, verification, synthesis, HW/SW co-working) Familiar with at least one of the followings: Wi-Fi, Bluetooth, MAC architecture, and Security engine architecture Experience with tapeout of new product No travel required

About Marvell . Your Team, Your Impact Marvells data center engineering group is a leading provider of innovative storage technologies, including ultra fast read channels, high performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid state drive (SSD) electronics markets and accelerator solutions. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems. What You Can Expect Design and execute post silicon validation tests for SSD Chipsets, during R&D processes. Develop, port and execute bare metal SW to validate Storage SoCs. Job will involve Pre and Post Si testing of the bare metal functionality of the Storage SoC, including performance, and power. The candidate will also review and prepare test plans and test results documentation. Develop testing and benchmarking applications. Analyze the test results and generate professional validation reports. Provide technical support to Field Application Engineers who support customers. Provide technical support to Test Engineers who design tests for mass production. What Were Looking For We are looking for hardware validation/applications engineer with experience in Solid States Drive. Proficient in C/C++ , Arm Assembly , 64 bit Arm CPU architecture. Experience in Firmware Development under Bare Metal/Linux Environment and Debugging on SoCs for embedded Applications Understanding of SSD controller is preferred Experience in interfaces like NAND/PCIe/NVMe/DDR is a plus Good communication skills in English, written and spoken. Candidate should be flexible, proactive and have the ability to work in a team Should be able to work on a given task independently Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

About Marvell . Your Team, Your Impact Marvells data center engineering group is a leading provider of innovative storage technologies, including ultra fast read channels, high performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid state drive (SSD) electronics markets. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems. What You Can Expect Development, porting, execution, and debug of bare metal SW on multiple SSD blocks to validate proper functionality. Create, maintain and improve code to support new features and standards. Work with Design, FW, and Validation teams to debug any issues found and find root cause on failure cases. Create and review tests plans and prepare test result documents to be shared internally/externally. Create tests to measure performance, throughput, and power of multiple SoC blocks. What Were Looking For Bachelors degree in Software, Computer or Electrical Engineering, and at least 3-5 years professional experience and/or Masters degree in Software, Computer or Electrical Engineering, and at least 2-3 years professional experience, in following domains - Pre-Si Validation, Post-Si Validation, Stress & PVT testing. Excellent C/C++ SW development skills, a good understanding of embedded SW development, Linux and basic knowledge of ARM/RISC micro-processor or SOC architecture. Working knowledge of DDR, SPI, PCIe, NVMe, is a plus. Experience with embedded SW development and proven debug abilities and skills. Familiar with typical lab tools: Emulators, Oscilloscopes, Logic Analyzers. Able to work across disciplines and manage time across several demands. Excellent written and oral communication skills (English). Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Expertise in Electrical Bench Characterization Expertise in Electrical performance validation: PCIe Gen5, LP / DDR4 / 5, Ethernet (10G/25G) Expertise in BERTs, VNAs, Oscilloscopes, Signal Integrity Expertise in debugging silicon / platform issue Expertise in data analysis / statistics Expertise in Test scripting (LabVIEW / Python preferred) Expertise in test automation Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit.

We are seeking a highly motivated and skilled Design Verification Engineer with a strong background in UVM, SystemVerilog , and IP-level verification . The ideal candidate will be responsible for developing and executing robust testbenches, simulation, and debugging strategies to ensure first-time-right silicon. Key Responsibilities: Develop and maintain UVM-based verification environments for IP-level testbenches. Perform RTL and Gate-level simulation and debug functional issues. Define and execute comprehensive test plans to validate functional correctness. Integrate and verify AMBA bus protocols such as AHB and AXI. Develop and close assertions and functional coverage to meet verification completeness. Write reusable SystemVerilog assertions (SVA) and functional coverage models. Collaborate with design, architecture, and verification teams to debug and resolve complex issues. Utilize scripting languages ( Shell, Perl, Python ) to automate flows and enhance productivity. Participate in regular code reviews and contribute to verification process improvements. Communicate effectively across cross-functional teams and global engineering groups. Required Skills & Experience: Strong expertise in UVM and SystemVerilog for testbench development. Solid experience in RTL and gate-level simulation and debug . Hands-on experience in test planning, writing, and executing test cases . Good working knowledge of AHB/AXI bus protocols . Proficient in assertion-based verification and coverage development/closure . Working knowledge of C programming and scripting using Shell, Perl, or Python . Excellent communication, problem-solving, and team collaboration skills. Prior experience with IP-level DV and delivery is a must. Interested can share resume on Shubhanshi@incise.in

Responsibilities : - Develop and execute comprehensive verification plans for complex IP blocks and SoCs, including microarchitecture, functional, and performance verification.- Design and implement high-quality testbenches using industry-standard methodologies (e.g., UVM, OVM).- Develop and maintain test suites, including directed tests, constrained random tests, and coverage-driven tests.- Debug and troubleshoot complex verification issues, analyze simulation results, and identify root causes of failures.- Collaborate closely with design engineers, architects, and other verification engineers to ensure timely and successful chip delivery.- Participate in design reviews and contribute to the design process.- Stay abreast of the latest verification methodologies, tools, and industry trends.- Document and report on verification progress, issues, and risks. Qualifications : - 4-7 years of professional experience in functional verification of complex digital designs (IP/SoC).- Strong understanding of digital design fundamentals and verification methodologies.- Expertise in developing and executing testbenches using industry-standard methodologies (e.g., UVM, OVM).- Experience with SystemVerilog, C/C++, and scripting languages (e.g., Perl, Python).- Good understanding of cache coherency protocols.- Experience with high-speed protocols (e.g., PCIe, DDR, Ethernet) is a plus.- Experience with UPF (Unified Power Format) and low-power simulation is a plus.- Excellent problem-solving, analytical, and debugging skills.- Strong communication and interpersonal skills.- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

Role & responsibilities Job Responsibility As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, test cases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with the RTL/uArch team. Job Requirements Experience with block level, cluster level or chip/SoC level verification. Should be a self-starter. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Post silicon support Preferred candidate profile

Experience in working on validation of ASIC/SoC products. Knowledge of post-silicon features & functional validation for BSPs and Linux Device Drivers. Knowledge of Test case development & implementation for IP's features. Expertise in protocols/interfaces such as USB, PCIe, I2C, SPI, UART, and Ethernet. Knowledge of Software Development & Testing Life Cycles. Strong knowledge of C, Python, Shell, and Bash Scripting. Strong knowledge of Linux Kernel, Boot-Up Process, Linux-Internals, and System Calls. Understanding of Schematics and PCB board design. Experience with version control software such as GIT. Excellent Communication and learning skills.

ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch for block and cluster level environments. Maintain and enhance existing DV environments. Develop test plans and tests for qualifying design at block, and cluster level environments with mix of constraint random and directed stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance. Support testing of design in emulation. Minimum Qualifications Bachelors Degree in EE, CE, or other related fi eld. 5+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying complex blocks and/or clusters for ASIC. Experience building test benches from scratch, hands on experience with SystemVerilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Looking for a talented and experienced Developer to join our team. This role focuses on developing and maintaining Linux device drivers, with a specific emphasis on Ethernet and various other hardware interfaces. Job Summary The Developer - Linux Device Driver will be responsible for designing, developing, testing, and debugging device drivers for Linux-based systems. This role requires deep technical knowledge of Linux kernel internals, hardware interfaces, and driver development best practices. Responsibilities Design and develop Linux device drivers for various hardware interfaces. Debug and resolve complex issues related to device drivers. Optimize driver performance and ensure system stability. Collaborate with hardware and software teams to integrate drivers into systems. Participate in code reviews and provide technical feedback. Maintain and update existing drivers as needed. Document driver designs and implementation details. Qualifications Bachelor's degree in Computer Science, Electrical Engineering, or a related field. 5+ years of experience in Linux device driver development. Strong knowledge of Linux kernel internals and driver architecture. Knowledge of processor architectures for ARM or RISC-V Knowledge of processor architectures for ARM or RISC-V Experience in debugging with JTAG, Signal Analyzers etc. Proficiency in C programming language. Experience with Ethernet drivers and networking protocols. Familiarity with various hardware interfaces (e.g., Ethernet, PCIe, USB, I2C, SPI). Experience with debugging tools and techniques. Excellent problem-solving and analytical skills. Strong communication and collaboration abilities. Preferred Qualifications Experience with real-time operating systems (RTOS). Knowledge of device tree and ACPI. Contributions to open-source Linux projects. Experience Areas The following table describes some of the areas of experience expected of a Developer - Linux Device Driver. Description Ethernet : Development and debugging of Ethernet drivers, including network protocols. PCIe : Driver development for PCIe-based devices. USB : Experience with USB device drivers. I2C : Development of drivers for I2C communication. SPI : Knowledge and experience with SPI drivers. Debugging : Experience using debugging tools and techniques for device drivers.

JD Highlights: 6 to 10 years of relevant experience Electrical performance: PCIe Gen5, LP/DDR4/5, Ethernet Tools: BERTs, VNAs, Oscilloscopes Signal Integrity basics, hands-on debug Test scripting and automation (LabVIEW/Python preferred) Cross-functional collaboration

Expertise in ASIC verification, Expertise in System Verilog and UVM, Verilog. Experience in technical lead , leading a team of 2-5 engineers. Expertise in IP level verification, testbench architecture development, Testbench component developments. Expertise in coverage closer, code coverage, functional coverage Experience in Gate level simulations. The candidate should be able to define verification plan, create testbenches, testcases,gate level simulations etc independently. Knowledge on serial protocols PCIe, USB, UFS Knowledge on scripting languages like Python, Perl etc. Keen on continuous process improvement to improve Quality and time

Job Overview Tessolve seeks a dynamic and experienced Bench Char Engineer to bepart of the Bench Char team. The ideal candidate will have a strong technicalbackground and the ability to establish and nurture long-term clientrelationships. This role involves working closely with cross-functional teamsto achieve organizational goals. Job Location :Electronic -City, Phase II, Bangalore. What you ll do v Support in characterization ofdevice performance and prepare characterization report v Write and debug test programs fordevice characterization v Analyze test data, perform rootcause analysis of device failures, and define solutions v Recommend improvements to devicestructure based on characterization data v Develop new techniques to streamlinecharacterization process v Identify and resolve deviceperformance issues promptly v Present test results in accurate andclear manner v Assist development and manufacturingengineers in designing and developing new devices; v Mentoring junior characterizationengineers and lab technicians; Who you are Bachelors in Electronic engineering or (related field) Experience with High speed PCIe, SEREDES, DDR, USB and Power IC characterization and Electrical Parameter validation of Silicon is a strong. Experience in PMIC modules BUCK,BUCK-BOOST, BOOST and LDO Electrical Parameters Measurement. Good knowledge analog and digital electronic engineering fundamentals Effectively wield the electronics tools: Oscilloscopes, Multimeters, Waveform Generators, Power Supply and Spectrum analyzers Knowledge of communication interfaces (I2C, UART, SPI, USB) Knowledge of PCB in layout and schematic readability experience Software development skills in one of the following languages Python, MATLAB, NI LabView, NI TestStand Able to work in a team. Fluent written and verbal English is essential. Tessolve Semiconductor Private Limited, as well as its affiliates andsubsidiaries ( Tessolve ) does not require job applicants to make anypayments at any stage of the hiring process. Any request for payment inexchange for a job opportunity at Tessolve is fraudulent and should be ignored.If you receive any such communication, we strongly advise you to refrain frommaking any payments and to promptly report the incident to us athr@tessolve.com. Tessolve is not responsible for any losses incurred due to suchfraudulent activities