458 Pcie Jobs

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based onImplementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We make real what matters. This is your role! Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and improve these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will cooperate with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds We seek a graduate with an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute Phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. We value sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. Knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a phenomenal teammate, resilient and candid, Enjoy learning new things and build knowledge base in new area. We’ve got quite a lot to offer. How about you This role is based in Noida but you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the world’s most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-EDA #LI-Hybrid

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications: Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or schoolwork/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6-8 years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 5-7 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of related work experience. Minimum Qualifications- 4+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth experience. 4+ years of experience in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators, and coverage tools. 4+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE. 4+ years of experience in OVM/UVM for developing verification test benches and constrained random verification. Preferred Qualifications- Experience with PCIe, Power Management, Ethernet, Network packet processing. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : We are seeking a passionate and experienced Embedded Firmware and Driver Engineer to design, develop, and optimize low-level embedded software for Intels AI accelerators and GPUs. In this role, you will collaborate with a cross-geo team to create world-class embedded software solutions. Your responsibilities will includeDesigning, developing, and maintaining bare-metal firmware for ARC-based processors. Creating and managing Boot ROM and Boot loader systems. Developing and maintaining RTOS-based device drivers. Delivering new features requested by Cloud Service Providers. Solving complex technical problems and contributing to innovative solutions. Collaborate with hardware, system, and driver teams for feature definition and end-to-end delivery Qualifications: Minimum qualifications: Bachelors degree in computer science, Electrical Engineering, or a related field with at least 8 years of relevant experience in Embedded Software Design and Development. Proficiency in ARC or other low-power controller architectures. Expertise in C programming and basic understanding of assembly language. Deep understanding of real-time systems, interrupt handling, and RTOS (e.g. Zephyr) Proven experience in writing boot firmware Familiarity with communication protocols such as SPI, I2C, and UART. Excellent analytical and problem-solving skills, with the ability to manage stakeholders and collaborate across geographies. Exceptional written and oral communication skills. Hands-on experience in developing and integrating RTOS based device drivers. Preferred qualifications: Knowledge of interfaces like I3C, PCIe, CXL, and protocols such as SMBUS/PMBUS and MCTP/PLDM. Experience in pre-silicon emulation, simulation, and FPGA platforms, along with debugging tools like Lauterbach and protocol analyzers. Knowledge in one or more of the following areasConfidential Computing, UCIe, or HBM technologies. Understanding of DVFS algorithms, AVS, and thermal management strategies Familiarity with secure boot, firmware update mechanisms, and memory management and open-source projects like buildroot-external. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications: Bachelor Degree in Electrical and Electronics Engineering or Masters Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or school work/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 10+ years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9+ years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 8+ years of related work experience.Minimum Qualifications- 9+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth know how. Solid work experience in designing, verifying, and validating complex hardware systems. Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, and Python. Proficient in debugging SOC, fabric, NOC, memory, various protocols like PCIE or Ethernet, or other complex ASIC designs. Knowledge of advanced computer architecture and micro-architecture concepts. Experience with writing directed and random test cases. Experience with design verification and validation methodologies and strategies. Good communication skills, and a team player. Able to work independently in a fast-paced team and environment. Desired - Deep knowledge of system architecture including CPU, Data path packet processing flows , Boot Flows, fabrics, interconnects, NOC, memory sub-systems, I/O peripherals (UART/SPI), bus protocols (AXI/APB), PCIE, Ethernet, DMA etc. Experience with boot, reset, clock and power management. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities -Linux application programming Linux device driver development Embedded C, MMU, Cache policies Excellent debugging skills at kernel and user space and exposure to different debugging tools Knowledge on PCIe, Ethernet, TCP, I2C protocols, DMA framework is a plus. Make files Skills Must have Candidate should have 5-8yrs experience Proficient in C and embedded systems. Experience in Linux driver development (PCIe/USB/Ethernet) and application development. PCIe driver development experience. DMA client/controller driver development experience Hands-on experience with Configuration Management tool like GIT, Perforce. Have an interest to constantly learn and share new findings. A quality mindset, ability for strategic thinking and a drive to always improve. Self-motivated Nice to have B.tech/M.Tech in CSE/IT/ECE/EEE/E&I Other Languages EnglishB2 Upper Intermediate Seniority Regular

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Responsible for developing & testing of software Responsible for generating documents, such as Spec, design, user-guide, API spec, etc., Skills Must have Candidate should have 7+ yrs experience Experience: Experience in designing complex multithreaded Performant SW Experience in designing SW API interfaces. Experience in C/C++ programming Experience with Multi-threaded software development in Linux environment Experience with Embedded IP subsystems e.g. Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA Experience with development of software targeted for x86, standalone and RTOS platforms Experience in low level driver development, register interface programming, general algorithms and data structures, bootloaders/Uboot Experience working with and integrating open-source software Strong debugging skills at device and board level using JTAG debuggers Experience in Software programming for FPGAs is an advantage Scripting language experience like Perl, Python or TCL Nice to have Excellent interpersonal, written and verbal communication skills Excellent communication, problem solving and analytical skills EducationB.tech/M.Tech in CSE/IT/ECE/EEE/E&I OtherLanguagesEnglishB2 Upper Intermediate SenioritySenior

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Owning and Driving execution of subunits/unit level Verification Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Work with logic and development teams to identify test scenarios, create test plans and execute the scenarios. Work with IBM Verification community to improve Verification methodology. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12 + years of experience in Functional Verification of processors or ASICs. Minimum 9+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading teams Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification. Good understanding of the Server System

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Candidate should have experience in Software development, tools development role, firmware development role or validation tools development.Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He/She will be working on processor Bringup Activities and own key debugs during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must work on coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Technical ExpertiseVery proficient in C programming, Strong Scripting skills. Over 5 years experience in hands on Software development using C, C++. Computer Architecture KnowledgeIn-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. Multi-Processor Cache CoherencyExperience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Operating Systems and ConceptsAtleast 2 years experience with Multithreading, context switching, memory management related development Preferred technical and professional experience IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience) ARM architecture RISC V architecture Spike simulator experience, QEMU simulator

you will: Develop and integrate products deployed by leading service providers worldwide. Collaborate with a vibrant, BU-wide technical community to exchange ideas and innovate on next-generation technology. Explore opportunities for personal growth while mentoring colleagues and working on cutting-edge technologies. As a key member of this team, you will: Work alongside seasoned engineers to architect, design, and develop some of routers and solutions for the world's largest service provider, web centers, and enterprises. Contribute to the evolution of these systems to support exciting new customer business paradigms. Interact and collaborate with some of the finest talent in the industry, making work both fun and challenging. Engage with other groups such as Product Management, Marketing, Sales, Customer Support, and Advanced Services. Who You Are: You possess: In-depth knowledge of C and a solid understanding of Python. Extensive experience in a Unix/Linux-based development environment. Excellent coding, automation, and debugging skills. Strong teamwork and communication skills. Familiarity with hardware architectures such as PCI, PCIe, DMA, I2C, SPI , NPUs/DPUs and processors like x86, AMD, and ARM . Experience with board bringup is a plus. Experience with emerging technologies such as AI/ML and cloud computing is a plus. Experience and Qualifications: Experience: 9 to 12 years in embedded firmware development. Education: BE/B.Tech/ME/M.Tech/MS in CS/EE/IT/ECE, MCA, or similar education. Proven ability to derive design and code based on technical standards and write comprehensive, focused design documents. Experience in developing software/firmware for networking equipment. Excellent knowledge of software architecture and system design.

Overview Lead Verification engineer Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Bachelor’s/ Master’s degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platformsUVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Bachelor’s/ Master’s degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platformsUVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 15+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skil Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Exp -3-6 yrs with Bachelors or Masters in Engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a VLSI engineers who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills 2-4 yrs experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 2 - 4 yrs of experience is preferred

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at SOC level. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronic with 2+ year experience in verification domain. Prior work experience on IP level or Soc level. Good understanding of process Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills Experience in Hifi Processor, Soundwire interface, ANC, DMA, I2S verification experience is a Plus. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12-15 years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. SOC level Mixed Signal and High Speed Interfaces verification Engineer Experience of 1 year to 6 years in Design Verification Responsible for RTL and GLS level validation at SOC. Post Silicon validation support Familiarity with basic concepts of SV, UVM and C-based test case bringup. Understanding of GLS simulations and debug is a plus. Good in communication. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Bachelors /Masters degree in Engineering Relevant experience of 6+yrs in any of the mentioned domain - Verification/ Emulation/ Validation Verification: Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce FPGA Emulation : Familiarity with Verilog/Vhdl and General Digital Logic Design concepts Knowledge of system-level architecture including buses like ARM processor bringup, AXI/AHB, bridges, memory controllers such as DDR/Nand. Knowledge of peripheral emulation like PCIE/USB is a plus. Strong working knowledge of UNIX environment and scripting languages such as Perl or shell Working knowledge XILINX Virtex FPGA architecture and experience with ISE tool flow Pre/Post silicon Validation: ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational 2+ years of experience with a Bachelors/ Masters degree in Electrical engineering