Principal Engineer Infineon Technologies

12.0 - 14.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Expert in implementing Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. In your new role you will: Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at/TDF/Bridging/Cell-aware/iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JT...

Posted 3 weeks ago

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Senior DFT Engineer Truechip

0.0 years

0 Lacs

delhi, india

On-site

Education BE/ BTech (Electronics/ Electrical/ Electronics and Communication) MS or MTech would be preferred The Candidate Is Expected To Have Worked On Scan insertion and DRC cleanup Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading. Memory testing. Should also know the algorithms. Should also have knowledge about diagnostics. JTAG or P1500 or other interface mechanism Desirable competencies The Candidate Is Expected To Have Exposure To Compression tools is highly desirable LBIST, mixed-signal testing, logic equivalence Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required. Bridge fault detection is desirable ATE exper...

Posted 1 month ago

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DFT - MBSIT AND ATPG Modernize Chip Solutions (MCS)

4.0 - 8.0 years

0 Lacs

karnataka

On-site

You should have a minimum of 4 years of experience in the field. You must be proficient in using Synthesis and netlist validation tools, particularly LEC and Spyglass checks, as well as scan insertion and DRC debug. It is essential to be well-versed in both Synopsys and Mentor Graphics DFT flows. Your expertise should also include experience in Scan Compression for Hierarchical and Modular EDT, ATPG, and Coverage debug, along with the ability to manage multiple clock domains and familiarity with the OCC flow. You should have practical experience in BIST and BISR insertion and Validation with SMS and MBIST Architect. Hands-on experience with JTAG, IJTAG, and SSN is required. You should be fam...

Posted 1 month ago

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