153 Ovm Jobs - Page 5

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project ? Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt ? ? Mandatory Skills: ASIC Design. Experience3-5 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Wipro Limited (NYSEWIT, BSE507685, NSEWIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role _x000D_ Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? _x000D_Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project ? _x000D_ Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt ? _x000D_ ? _x000D_ Mandatory Skills: ASIC Design_x000D_. Experience3-5 Years_x000D_. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

As CPU/Processor Nest Verification Lead, you will be responsible for the pre-silicon functional and performance verification of our chipsets, covering the CPU core, cache/nest subsystem, memory hierarchy, and other on-silicon IP used in our next-generation IBM Power Systems offerings. You will use state-of-the-art techniques to simulate and verify the designs of these custom microprocessor-based systems. The job uses both hardware and software engineering skills, and entails creating environments and methodologies for simulating the VHDL input, as well as analysis and problem debug. Verification is performed at various levels within the design hierarchy. A background in Electronics / Micro Electronics / Computer Science with strong programming skills is required. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise As a CPU/Processor Nest Verification lead, you will play a pivotal role in the pre-silicon functional and performance verification of our cutting-edge chipsets. Your responsibilities will cover a spectrum of critical areas, including the cache/nest subsystem, interrupt, Fabric, memory hierarchy, and various on-silicon IP integral to our upcoming IBM Power Systems offerings. Leveraging state-of-the-art techniques, you will be at the forefront of simulating and validating the designs of these bespoke microprocessor-based systems and providing technical guidance to junior/mid-level engineers in the team. Key Duties: Verification Environment OwnershipTake charge of the verification environments for microprocessor components, contributing significantly to the identification of functional and performance issues before silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes. Documentation and CommunicationThoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Communicate progress effectively, keeping team members and stakeholders informed of milestones achieved and potential challenges encountered.Lead the development of the verification plans, environment, testbenches and writing testcases for the Cache Coherency Transport Interconnect Fabric in IBM Server Processors. Technical leadership Providing Technical leadership to the senior/mid-level engineers who will be working closely with you. Stakeholder management Managing and influencing stakeholders technically, periodic update in status meeting/technical forums. Functional Verification Experience: 15+ years of extensive experience in functional verification of processors, demonstrating a deep understanding of verification methodologies and technically leading a large team. Computer Architecture Knowledge: Good understanding of computer architecture, including Processor core design specifications, Coherency and Cache Designs, Processor IO subsystem, Interrupt architecture, with expertise in at least any one of the above domains. Multi-processor Cache Coherency Transport Fabric Experience in functional verification of system level Coherency Transport Network designs and ways to stress verify them. Strong programming skills Proficiency in C++, Python scripting or similar languages. Preferred technical and professional experience Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL and general computational logic design and verification concepts. Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design. Experience in specifying and developing the verification infrastructure for verifying processor based designs. Minimum one full life cycle experience of a processor/SoC verification flow with focus on Coherency Transport Interconnect/Fabric Verification. Knowledge of system-level architecture including buses like AXI/ACE/CHI, AMBA interconnects

Role & Responsibilities : As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verification plans, environment, testbenches and writing testcases to verify Cache structures & protocols in processor. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. . Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Professional and Technical Expertise : 9 + years of experience in Functional Verification of processors or ASICs. 3+ years of experience in the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor Cache (L2/L3) Coherency, Memory Hierarchy Verification Minimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Cache Coherency Verification Developed test-plans and test strategies for IP/unit/block level verification of Cache Coherency structures in processor/SoC Good object-oriented programming skills in C++/SV, scripting languages like Python/Perl. Knowledge of functional verification methodology like UVM/OVM Knowledge of HDLs (VHDL/Verilog) Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenarios, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Additional skill Stress testing and ability to identify corner case scenarios.

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Experience in assertions development/closure, constraint randomization, functional and code coverages, formal verification Experiences in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills We re doing work that matters. Help us solve what others can t.

Role: AMS Verification Engineer / Sr. Engineer Experience required: 5-15 years Work location: Pune, Bangalore, Hyderabad, Chennai, and Noida Minimum 5 Years of overall experience in ASIC Verification Should have worked on AMS Verification for a minimum of 2 years Develop and execute verification plans for AMS designs. Create test benches and run simulations using tools such as Cadence Virtuoso, Spectre, or AMS Designer. Verify mixed-signal blocks (e.g., ADCs, DACs, PLLs) and ensure proper analog-digital interaction. Debug and resolve design issues in collaboration with design teams. Document verification results and ensure compliance with design specifications. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Role: ASIC Verification Engineer Experience Required: 5-15 Years Work location: Bangalore, Hyderabad, Chennai, Ahmedabad, and Pune Minimum 5 years of experience in System Verilog HVL. Minimum 5 years of experience in OVM/UVM/VMM/Test Harness. Hands-on experience in developing assertions, checkers, coverage, and scenario creation. Must have executed at least 2 to 3 SoC Verification projects Experience in developing test and coverage plan, verification environment and validation plan. Knowledge of at least one industry standard protocol like Ethernet, PCIe, MIPI, USB, or similar is required. Review and Audit participation. At least 1 year of experience in handling a team for the senior roles Define/derive the Scope, Estimation, Schedule, and Deliverables of the proposed work. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Mirafra is hiring!!! Hardware (HW) Verification Engineer Location: Hyderabad Experience: 5 to 10 Years Job Description: Mirafra Technologies is hiring experienced Hardware Verification Engineers to work on top-tier SoC verification projects. The ideal candidate will have strong UVM/SystemVerilog expertise and hands-on experience with FPGA and protocol-level testing. Responsibilities: Develop SV/UVM testbenches at Top/Sub-system/Block-levels Drive creation and execution of test plans and test specs Document verification phases: user guides, test reports, and execution logs Contribute to verification architecture and methodology development Required Skills: Strong programming skills in SystemVerilog and UVM Protocol verification experience: Ethernet, PCIe, SPI, I2C, USB Hands-on hardware testing experience using logic analyzers, traffic generators Exposure to FPGA verification and Xilinx tools Solid debugging skills at both device and board level Proficiency in scripting languages: Perl, Python, TCL Strong interpersonal, communication, and analytical skills Apply Now or send your resume to swarnamanjari@mirafra.com Note: This is a client-based selection process .

Job Title: Design Verification Engineer Location: Hyderabad Experience: 3 to 8 Years Job Description: Mirafra Technologies is looking for experienced Design Verification Engineers to join our team in Hyderabad . This role involves a mix of IP-level ownership, feature enhancement, and debug responsibilities. Key Responsibilities: Own design verification at the IP level Plan and execute feature additions and mode re-enablement for specific design variants Perform bug fixes and analyze regression signatures Minimum Qualifications: Proficient in SystemVerilog, UVM, UVM_REG , and advanced debugging techniques Experience reading specifications and developing comprehensive test plans Expertise in building monitors, scoreboards, sequencers, and sequences Skilled in using scripts and verification methodologies to enhance bug detection Strong understanding of functional verification , including test planning, testbench development, stimulus generation, checking, and functional coverage Comfortable with build checks , working with large testbenches , coverage analysis , and adding/enabling debug mechanisms Proactive approach to analyzing failures and identifying root causes Apply Now or send your resume to swarnamanjari@mirafra.com

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

verification experience in SV, UVM, DDR, serdes high speed protocol, PCIE

SENIOR VERIFICATION ENGINEER – SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware Location - Bengaluru,Chennai,Hyderabad,Noida

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Location : Company Name: Mirafra Technologies Positionskill set : PCIE Experts (Design Verification) Location: Hyderabad Experience: 6 to 12 Years Open Positions: 8 Notice Period: 0 to 40 Days Preferred Job Type: Full-Time Selection Type: All offers are client selection-based Location: Hyderabad/Bangalore Job Description: Mirafra is hiring experienced PCIE Verification Engineers for exciting opportunities with leading semiconductor clients in Hyderabad. If you're passionate about solving complex verification challenges, we want to hear from you! Key Responsibilities: In-depth understanding of verification flows and methodologies Hands-on experience with complex testbenches/models in Verilog, SystemVerilog, or SystemC Strong debug skills and a problem-solving mindset Functional and SoC-level verification, including emulation exposure Proficiency in SystemVerilog, PLI/DPI interfaces, C/C++, Perl/Shell scripting , and assembly language Experience with OVM/UVM methodologies Ability to work collaboratively in a team environment Good communication and interpersonal skills Preferred Skills: Background in x86 or ARM architecture-based SoCs Experience in SoC/IP performance verification is a plus Apply Now: If you meet the above requirements and are available within 0 to 40 days, send your resume to: [swarnamanjari@mirafra.com] or Click the apply button

Responsibilities: SoC integration/scenario/performance verification including CHI, DDRx/LPDDRx, and AI accelerator blocks in RTL. Develop test plans, SystemVerilog/Verilog testbenches, and C-based embedded tests. Collaborate with cross-functional teams architecture, design, performance, silicon validation, FPGA, and board teams. Plan, track and report verification tasks to management. Skills & Experience Required: Strong knowledge of Verilog/SystemVerilog HDL. Hands-on experience in SoC verification using embedded C/C++/assembly (ARM preferred). Experience in UVM/OVM, emulation, formal verification, UPF/Power-aware verification. Expertise in GLS, DFT/DFD, CDC (Clock Domain Crossing). Familiar with ARM SoC boot flows, cache coherency, SoC verification flow & strategy. Scripting experience in Python, Perl, Tcl, Shell. Excellent debugging and problem-solving skills.

Responsibilities : - Develop and execute comprehensive verification plans for complex IP blocks and SoCs, including microarchitecture, functional, and performance verification.- Design and implement high-quality testbenches using industry-standard methodologies (e.g., UVM, OVM).- Develop and maintain test suites, including directed tests, constrained random tests, and coverage-driven tests.- Debug and troubleshoot complex verification issues, analyze simulation results, and identify root causes of failures.- Collaborate closely with design engineers, architects, and other verification engineers to ensure timely and successful chip delivery.- Participate in design reviews and contribute to the design process.- Stay abreast of the latest verification methodologies, tools, and industry trends.- Document and report on verification progress, issues, and risks. Qualifications : - 4-7 years of professional experience in functional verification of complex digital designs (IP/SoC).- Strong understanding of digital design fundamentals and verification methodologies.- Expertise in developing and executing testbenches using industry-standard methodologies (e.g., UVM, OVM).- Experience with SystemVerilog, C/C++, and scripting languages (e.g., Perl, Python).- Good understanding of cache coherency protocols.- Experience with high-speed protocols (e.g., PCIe, DDR, Ethernet) is a plus.- Experience with UPF (Unified Power Format) and low-power simulation is a plus.- Excellent problem-solving, analytical, and debugging skills.- Strong communication and interpersonal skills.- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties include: Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology Build pseudo-random tests to verify and get to full Functional coverage Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture. Drive improvements in Verification in terms of quality and efficiency. Requirements: Bachelors degree in Electrical Engineering or related degree and 8+ years related experience or Masters degree in Electrical Engineering or related degree and 6+ years related experience 6+ Years of experience writing and debugging complex test benches Must have deep understand of all aspects of Verification from building Testbenches, developing Test plans and pseudo-random tests, Functional coverage. Must have proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM Should have exceptionally good command over fundamental OOP principles. A good understanding of a complex protocol like PCIe or other multi-layered protocol Capability to work independently and deliver. Knowledge of PCI Express protocol is desired Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties include: Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology Build pseudo-random tests to verify and get to full Functional coverage Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture. Drive improvements in Verification in terms of quality and efficiency. Requirements: Bachelors degree in Electrical Engineering or related degree and 8+ years related experience or Masters degree in Electrical Engineering or related degree and 6+ years related experience 6+ Years of experience writing and debugging complex test benches Must have deep understand of all aspects of Verification from building Testbenches, developing Test plans and pseudo-random tests, Functional coverage. Must have proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM Should have exceptionally good command over fundamental OOP principles. A good understanding of a complex protocol like PCIe or other multi-layered protocol Capability to work independently and deliver. Knowledge of PCI Express protocol is desired .

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0270511 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 3 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 6+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Act as focal point between design and tool vendors for issues and feature enhancements. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure Monitoring and improve existing simulation environments and simulation efficiency. Experience with Performance Validation of GPUs and automation framework using Python is desirable Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 17 Days Ago job requisition idJR0274344 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications.Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to micro-architecture specifications.Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.Replicates, root causes, and debugs issues in the pre-silicon environment.Finds and implements corrective measures to resolve failing tests.Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.Maintains and improves existing functional verification infrastructure and methodology.Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum Qualifications:BS with 10+ years/MS with 8+ years industry experiencesExperience on Pre-Si validation on Emulation, preferably Zebu.Experience on validation at MCP.Experience with pre-Si verification with System Verilog OVM/UVM on content development Scripting languages such as Python, Simics.Good understanding of RTL, Verilog, VHDL.Preferred Qualifications:Experience with Synopsys simulation and coverage tools.Assertion based verificationRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Perform verification for high-speed FPGA digital design using UVM/OVM for complex mathematical and control logic algorithms. Developing Verilog/VHDL code. Full testing of FPGA design which include testing of complete design with PS.