Formal Verification Engineer ACL Digital

4.0 - 6.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Title: Formal Verification Engineer Location: Bangalore Experience: 4+Years Job Type: Full-time Industry: Semiconductor / ASIC Design / EDA Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering Job Description: We are looking for a highly motivated Formal Verification Engineer to join our Design Verification team. The candidate will be responsible for developing and executing formal verification strategies to ensure functional correctness of complex IP and SoC designs. Key Responsibilities: Define and implement formal verification strategies and plans. Develop formal properties and assertions for critical design blocks. Apply formal techniques such as property checking, s...

Posted 2 weeks ago

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Verification Specialist ACL Digital

8.0 - 10.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Senior Formal Verification Engineer (CPU) Experience : 8+ years Location : Bangalore Role Overview: Owns property-based formal verification of the CPU core, pipeline stages, and subcomponents with exhaustive proof goals. Key Responsibilities: Lead formal planning and methodology for control logic, pipelines, and memory subsystems Define safety and liveness properties, model check for corner case behavior Guide designers in writing formal-friendly RTL and assertions Analyze convergence issues, coverage gaps, and create abstraction models Integrate formal sign-off into project milestones Required Skills: 8+ years of formal verification experience with CPUs or processors Strong with JasperGold,...

Posted 2 weeks ago

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Verification Specialist ACL Digital

8.0 - 12.0 years

0 Lacs

karnataka

On-site

As a Senior Formal Verification Engineer specializing in CPUs, you will be responsible for the property-based formal verification of the CPU core, pipeline stages, and subcomponents with exhaustive proof goals. Your role will involve leading formal planning and methodology for control logic, pipelines, and memory subsystems. You will define safety and liveness properties, model check for corner case behavior, and guide designers in writing formal-friendly RTL and assertions. Additionally, you will analyze convergence issues, coverage gaps, and create abstraction models, while integrating formal sign-off into project milestones. To excel in this role, you should have a minimum of 8 years of f...

Posted 3 months ago

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