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Capgemini Technology Services India Limited logo
DFT/Design for Testability Capgemini Technology Services India Limited

5.0 - 12.0 years

4 - 8 Lacs

bengaluru, karnataka, india

On-site

Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBISTon complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing, integrating and verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high testCoverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functional teams interaction for issue resolution. Participate in dr...

Posted 1 day ago

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