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STA Engineer Capgemini

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

You will be responsible for performing chip-level floorplanning, partitioning, timing budget generation, and power planning. Additionally, you will execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation. Your duties will also involve handling block-level implementation from netlist to GDSII, driving timing closure for high-frequency blocks, and managing blocks with high instance counts (1M+). Moreover, you will ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification, applying signal integrity (SI) prevention and fixing methodologies, and conducting layout edits and physical design optimizations. F...

Posted 2 months ago

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