DFT - MBSIT AND ATPG Modernize Chip Solutions (MCS)

4.0 - 8.0 years

0 Lacs

karnataka

On-site

You should have a minimum of 4 years of experience in the field. You must be proficient in using Synthesis and netlist validation tools, particularly LEC and Spyglass checks, as well as scan insertion and DRC debug. It is essential to be well-versed in both Synopsys and Mentor Graphics DFT flows. Your expertise should also include experience in Scan Compression for Hierarchical and Modular EDT, ATPG, and Coverage debug, along with the ability to manage multiple clock domains and familiarity with the OCC flow. You should have practical experience in BIST and BISR insertion and Validation with SMS and MBIST Architect. Hands-on experience with JTAG, IJTAG, and SSN is required. You should be familiar with P1500 and have experience in managing wrapper cells and test integration. Knowledge of INTEST and EXTEST modes, as well as working knowledge on Cell Aware ATPG, is important for this role. Additionally, strong communication and Automation skills are a must for this position.,

Posted 1 week ago

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