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Design and Verification Engineer Acesoft Labs

1.0 - 6.0 years

6 - 12 Lacs

hyderabad

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Job Title: VLSI Verification Engineer Experience: 1 to 3 years Location: Hyderabad Job Description: We are seeking a highly motivated VLSI Verification Engineer with hands-on experience in circuit simulation, gate-level verification, and schematic analysis . The candidate will work on SPICE-based simulations, GLS with SDF back annotation, and transistor-level debugging to ensure design quality and sign-off readiness. Key Responsibilities: Develop, understand, and analyze block-level & memory schematics. Perform SPICE simulations (DC, transient) and correlate with gate-level models. Conduct gate-level simulations with SDF back annotation. Debug annotation issues, timing violations, and GLS fa...

Posted 1 day ago

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