2 Netlist Simulation Jobs

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1.0 - 3.0 years

0 Lacs

hyderabad, telangana, india

On-site

Semiconductor Design Engineer 1_INR Details: Experience: 1yrs to 3yrs. Location: Hyderabad JD: Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis. Experience in deciphering circuit behavior from schematics. Familiarity with circuit characterization, timing libraries - files and formats, timing arcs Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations. Familiarity with static timing analysis Hands-on experience in Gate level simulations with SDF back annotation. Debug SDF annotation issues and ensur...

Posted 1 month ago

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10.0 - 15.0 years

25 - 30 Lacs

bengaluru

Work from Office

We are hiring DV Contract Engineers with 10+ years of experience in UVM-based testbenches, netlist/gate-level simulations, and datapath blocks. Strong expertise in Cadence tools (Xcelium/Simvision) and scripting (Python/Shell) required. Required Candidate profile Experienced DV engineer with 10+ years in verification, UVM testbench, Cadence tools (Xcelium/Simvision), netlist & gate-level simulations, coverage closure, debugging, and scripting.

Posted Date not available

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