STA, Synthesis Wafer Space - An ACL Digital Company

4.0 - 8.0 years

0 Lacs

karnataka

On-site

You should have a strong understanding of EDA tools and flows, with specific experience in Tempus/Primetime. Your expertise should include timing closure (STA) and various timing closure methodologies. You will be responsible for pre/post-layout constraint development towards timing closure and collaborating with the design team to establish functional/DFT constraints. Additionally, you will need to integrate IP level constraints and define multi-voltage/switching aware corners. An understanding of RC/C model selection and expertise in abstraction techniques such as Hyperscale/ILM/ETM will be crucial for this role. You will also be expected to perform RC balancing and scaling analysis for full chip clocks and critical data paths. Proficiency in automation using PERL, TCL, and EDA tool-specific scripting is essential. Experience with DMSA at full chip level and developing custom scripts for timing fixes will also be required. Overall, the role demands a deep understanding of timing closure concepts, strong automation skills, and the ability to work closely with the design team to ensure successful implementation of constraints and fixes.,

Posted 2 days ago

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