General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/ Analog/ RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm SoC Verification Engineer The candidate will be responsible to own SoC Interconnect DV (Connectivity matrix, Coherency, Clock gating, Performance etc) during the project work. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams. Skillsets / Requirements : B.E/B.Tech/ M.E/M.Tech in Electronics with 7+ year experience in verification domain. Good understanding of Soc level verification testbench and flows. Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc. Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI. Solid hands-on working experience on System Verilog and UVM methodology. Expert in handling protocol BFM/ VIP integration and traffic sequence development. Experience in coding assertions and functional coverage bins. Qualcomm Power DV Engineer We are looking for passionate, highly motivated, and creative individuals to be part of our Power Verification team. As the power team member, you will work on projects that will define the next generation of Modem, Mobile, XR/VR and Automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's, cutting edge power optimization techniques, Functional safety aspects and many other leading technologies deployed in our Snapdragon chips. General Summary Qualcomm Power DV team is responsible for the verification of Power Controller sub-system that powers up/controls the clock/voltage/ operating level/power for the entire SoC. Along with the complex power controllers, the team is responsible for verification of various sensors and the respective controllers, Power limits management IPs and the IPs interacts with the external PMIC. In the role of Power Verification Engineer, you are expected to understand the Low power design functionality and verification strategies and driver the overall SoC low power verification. The Responsibilities Will Majorly Include Understanding of SoC power domains and HW programming guide sequences Develop test plan to verify all low power aspects across all modes of verification RTL, PA-RTL, PA-GLS and Formal Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Participate in post Si debug and bring-up activities Exploring innovative dynamic or static methodologies by engaging with EDA vendors Work with architects, designers, FPGA and post-silicon teams to ensure that the IPs are verified/validated thoroughly. Preferred Qualifications: Strong System Verilog/ UVM based verification skills & Experience with Assertion & coverage-based verification methodology Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Bus protocols (AHB/ AXI/APB) C/C++ with any ARM core knowledge Exposure to Formal/Static verification methodologies and Post-Si debugs would be excellent Good debugging and analytical skills. Good interpersonal skills, ability to work as an excellent teammate Excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization BTech/MTech with below years of experience in verification closure of complex Unit, Sub-system or SOC level verification. 5 To 12 Years of experience to lead Power DV of one or more SoCs Qualcomm SOC DV Engineer (MM) As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of our highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle.Minimum qualifications BE/BS degree in Electrical Engineering with 5+ years of practical experience Strong fundamentals in digital ASIC verification Experience in IP/SS/ SoC level verification of medium to high complexity design Knowledge of one or more of Multimedia design blocks such as Display/ Camera/Video/GFx Familiarity with system level HW and SW Debug techniques and Verification requirements Preferred qualifications MS degree in Electrical Engineering; 4+ years of practical experience Expertise in IP/SS/System level verification flows of one or more of Multimedia design blocks Familiarity with one or more of the bus standard interface protocols for Multimedia designs, such as DisplayPort/ HDMI/ CSI/DSI Exposure to ARM Core debugging techniques would be a plus Strong understanding of AMBA bus protocols A good understanding of the complete verification life cycle (test plan, testbench through coverage closure) Extensive knowledge in multiple testbench structures Exposure to FPGA and emulation platform debugs Proficiency in UVM, C/C++ Experience w/ PSS or higher-level test construction languages is an added advantage Knowledge of assertion-based formal verification is an added advantage Additional Job Description Roles and Responsibilities Define verification architecture, develop test plans and build verification environment Work with design team to understand design intent and bring up verification plans and schedules Verify Subsystems and Full SoC using advanced verification methodologies Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard Debug test cases and report verification result to achieve expected code/functional coverage goal Assist in silicon bring-up, debug and characterization Qualcomm SOC Verification Engineer (Debug) As verification engineer candidate will be responsible to own SoC Debug DV (Crash reset, Trace, debug infra etc) during project work. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams. Skillsets/Requirements : B.E/B.Tech/ M.E/M.Tech in Electronics with 7+ year experience in verification domain. Good understanding of Soc level verification testbench and flows. Working knowledge and design understanding of Debug architecture of a SoC which includes Crash flow, JTAG, Trace, triggers, monitors, Scandump etc. Exposure to Power aware simulations and Gate Level simulations Good understanding of processor based Soc level verification which includes Verilog, System Verilog and UVM based environment. Good understanding of AHB/AXI & ATB-AMBA protocol.
