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ASIC Digital Design, Staff Engineer Synopsys

4.0 - 9.0 years

5 - 7 Lacs

Hyderabad / Secunderabad, Telangana, Telangana, India

On-site

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What You ll Need: BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying verilog and system verilog design. Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC Experience of leading technically for Front end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred).

Posted 2 weeks ago

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ASIC Digital Design, Staff Engineer - RTL Design Synopsys

4.0 - 9.0 years

5 - 7 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

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Posted 2 weeks ago

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Senior Design Verification Engineers Synopsys

10.0 - 15.0 years

10 - 14 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

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What You ll Need: MSEE or BSEE with 10+ years of digital design and verification experience. Strong understanding of verification methodologies like System Verilog and UVM. Familiarity with RTL coding and design principles. Proficiency in scripting languages like Perl and Python for automation. Excellent debugging and troubleshooting abilities. Experience with test chip and full chip knowledge is an advantage. Proven leadership and team-building skills.

Posted 2 weeks ago

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