10.0 - 15.0 years

4 - 8 Lacs

Bengaluru, Karnataka, India

On-site

Job description You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites. Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. (30%) Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity. (25%) Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation. (30%) Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%) Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology (5%) Required Skills: ASIC Verification using System Verilog Experience in constrained-random verification is a strong plus Experience with verification methodology like OVM/VMM/UVM Perl/Tcl scripting is strongly preferred Experience verifying networking protocols such as Ethernet is desirable Strong problem solving and ASIC debugging skills MSEE or BSEE is required with at least 12 years of ASIC Verification Experience.

Posted 6 days ago

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Actimize Developer Ifintalent Global Private Limited

0.0 - 2.0 years

0 - 2 Lacs

Chennai, Tamil Nadu, India

On-site

Job Description Primary need to Configure and setup MSE 5.12.x packages Develop PL/SQL store procedure to process the data Perform Unit and Integration and non-regression testing Prepare Design Specification, Technical Specification Prepare the data requirement and mapping document Design and Configure RCM and AIS

Posted 2 weeks ago

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ASIC Digital Design, Staff Engineer Synopsys

4.0 - 9.0 years

5 - 7 Lacs

Hyderabad / Secunderabad, Telangana, Telangana, India

On-site

What You ll Need: BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying verilog and system verilog design. Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC Experience of leading technically for Front end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred).

Posted 2 months ago

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ASIC Digital Design, Staff Engineer - RTL Design Synopsys

4.0 - 9.0 years

5 - 7 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Posted 2 months ago

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Senior Design Verification Engineers Synopsys

10.0 - 15.0 years

10 - 14 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

What You ll Need: MSEE or BSEE with 10+ years of digital design and verification experience. Strong understanding of verification methodologies like System Verilog and UVM. Familiarity with RTL coding and design principles. Proficiency in scripting languages like Perl and Python for automation. Excellent debugging and troubleshooting abilities. Experience with test chip and full chip knowledge is an advantage. Proven leadership and team-building skills.

Posted 2 months ago

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