Job
Description
Key member of design verification team, which has both mixed-signal and digital design verification engineers. The candidate will be responsible for formulating verification strategies and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both INA and ADI. It is expected that he/she will be able to understand and influence other disciplines (analog/digital design) to achieve better all-round chip verification. The candidate is also encouraged to participate in cross company technical initiatives as we'll as patent and publish work where possible Requirements B.Tech/M.Tech with 8+ years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of analog/mixed-signal building blocks such as power management, ADCs, DACs, PLL, bandgap references, oscillators etc and related digital control and signal processing Demonstrated experience of verification plan, verification environment development and verification/debug of complex mixed signal products at chip-top level Experience of co-simulations with analog model/transistor level and digital RTL/Gate+SDFs, experience of circuit simulations with Spice/Fast Spice simulators Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe Responsibilities Come up with verification strategy for a product after going through product requirements and design specifications Interact with digital/analog leads to get agreement on verification strategy Create models for analog/mixed-signal blocks for chip-top verification, tradeoff accuracy Vs speed. Validate models against actual design (self-checking tests) Create verification plans, build verification environment, develop self-checking testcases. Bring up chip top mixed-signal verification environments (AMS and DMS DV environments) Deploy industry standard SV/UVM based metric driven verification approach Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV etc) for first pass silicon Support test and characterization teams in post-silicon validation Collaborate with CAD team to deploy next generation innovative design verification methodologies to reduce overall TTM, mentor junior DV engineers in the team Skill Set [Experience of following is desired, not all but most of them] Modelling of analog blocks - SV-RNM - Verilog-AMS - Schematic based structural models (macro models) - System C Familiarity with analog/mixed-signal design architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision Chip-top co-simulation with tools such as Cadence ADE/Cadence AMSD with Spectre as the analog solver and Xcelium as the digital solver Experience and debug with digital simulators such as Cadence Xcelium/Synopsys VCS Experience with Spice/Fast Spice simulators such as Spectre Ultrasim/APS/XPS Experience with SV/UVM (agent creation, env building, score-boarding, RAL etc) Experience with third-party IP integration Tracking of verification metrics and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager Experience with languages/tools/software relating to product development is an added advantage - C, C++, System C, AMS - Automation with scripting languages: Python/Perl/Shell etc - Embedded programming for on-chip micros or separate MCUs - Matlab/Simulink for system level simulations and modeling
