129 Modelsim Jobs - Page 4

? Do Consulting Execution An ambassador for the Wipro tenets and values, secures great feedback from multiple clients Consulting project Manager or equivalent coordinates teams of consultants, responsible for assuring quality of deliverables Flexible in approach, ability to coordinate resource with expertise in various areas Decisive and directive delivery focus with a can do attitude, demonstrates both hard and soft skills Coaches, mentors and motivates team and client staff, build trust and confidence through focus on quality and delivery Effective at engaging with clients, extracting information, e.g., developing facilitation and communication skills Responsible for ensuring project administration is up to date e.g., SoW, tagging, etc., Business development Ensures high levels of individual utilisation achievement in line with the levels expected as part of the goal setting process Consistently agrees personal extensions with client Demonstrates developing network of relationships with clients and provides required intelligence/insights to solve’ clients business problems Builds relationships with client peers and provides required intelligence/insights to solve clients business problems Leads smaller scale meetings with sales teams, leads proposal development to a high standard working with sales teams as appropriate Anchors market research activities in chosen area of work Consistently plays a major role in opportunity identification, raising potential pursuits to practice leadership team, helping them proactively in pursuits

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology.Absorbs learning from post silicon on the quality of validation done during micro architects development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Experience on Pre-Si validation on Emulation, preferably Zebu.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

? Do Consulting Execution An ambassador for the Wipro tenets and values, secures great feedback from multiple clients Consulting project Manager or equivalent coordinates teams of consultants, responsible for assuring quality of deliverables Flexible in approach, ability to coordinate resource with expertise in various areas Decisive and directive delivery focus with a can do attitude, demonstrates both hard and soft skills Coaches, mentors and motivates team and client staff, build trust and confidence through focus on quality and delivery Effective at engaging with clients, extracting information, e.g., developing facilitation and communication skills Responsible for ensuring project administration is up to date e.g., SoW, tagging, etc., Business development Ensures high levels of individual utilisation achievement in line with the levels expected as part of the goal setting process Consistently agrees personal extensions with client Demonstrates developing network of relationships with clients and provides required intelligence/insights to solve’ clients business problems Builds relationships with client peers and provides required intelligence/insights to solve clients business problems Leads smaller scale meetings with sales teams, leads proposal development to a high standard working with sales teams as appropriate Anchors market research activities in chosen area of work Consistently plays a major role in opportunity identification, raising potential pursuits to practice leadership team, helping them proactively in pursuits

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.This posting is for a position on the DMR IMH OOB Validation Team. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Experience with validation in both simulation and emulation environments. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of verification principles and coverage. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

? Do 1. Design and Develop solutions as per client??s specifications Work on different softwares like CAD, CAE to develop appropriate models as per the project plan/ customer requirements Test the protype and designs produced on the softwares and check all the boundary conditions (impact analysis, stress analysis etc) Produce specifications and determine operational feasibility by integrating software components into a fully functional software system Create a prototype as per the engineering drawings & outline CAD model is prepared Perform failure effect mode analysis (FMEA) for any new requirements received from the client Provide optimized solutions to the client by running simulations in virtual environment Ensure software is updated with latest features to make it cost effective for the client Enhance applications/ solutions by identifying opportunities for improvement, making recommendations and designing and implementing systems Follow industry standard operating procedures for various processes and systems as per the client requirement while modeling a solution on the software

? Do 1. Design and Develop solutions as per client??s specifications Work on different softwares like CAD, CAE to develop appropriate models as per the project plan/ customer requirements Test the protype and designs produced on the softwares and check all the boundary conditions (impact analysis, stress analysis etc) Produce specifications and determine operational feasibility by integrating software components into a fully functional software system Create a prototype as per the engineering drawings & outline CAD model is prepared Perform failure effect mode analysis (FMEA) for any new requirements received from the client Provide optimized solutions to the client by running simulations in virtual environment Ensure software is updated with latest features to make it cost effective for the client Enhance applications/ solutions by identifying opportunities for improvement, making recommendations and designing and implementing systems Follow industry standard operating procedures for various processes and systems as per the client requirement while modeling a solution on the software

JD FOR SAP MM1) Must have 2 3 years of SAP MM experience. 2) Able to do SAP MM configuration. 3) SAP MM certification will be added advantage. 4) Able to speak Hindi & English fluently. 5) Ready to work from Ramagundam Plant, RFCL for a minimum of 6 months to 1 year.

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : SAP Sales and Distribution (SD) Good to have skills : SAP CRM Billing Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Developer, you will design, build, and configure applications to meet business process and application requirements. Your typical day will involve collaborating with teams to develop solutions that align with business needs and requirements. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the team in implementing innovative solutions Conduct regular team meetings to ensure project progress Mentor junior team members to enhance their skills Professional & Technical Skills: -The incumbent will work in partnership with global & cross functional business/IT team. This position is responsible to design I/T solutions and support cross-functional/platforms solutions on global level in an attempt to match the capabilities of the current I/T technology with business needs. Specific responsibilities include identifying opportunities to enhance exiting operations, assuming leadership role on medium sized initiatives, develop solutions to complex problems. Analyze business/technical needs and translate process into practice through the current Information Technology tool sets. Identify opportunities to enhance existing operations using new IT technology as a replacement for legacy systems manual effort. Implement new cross-functional/platforms solutions through configuration interaction and creation of functional specifications and facilitate solution realization. Assume leadership role in a medium size initiative by playing the key contributor, facilitator or group lead cross functional teams. Conduct cost/benefit analysis through evaluation of alternative design approaches to determine best-balanced solution. Best-balanced solution is one that satisfies the immediate stakeholder needs, meets system requirements and facilitates subsequent change. Troubleshoot, investigate and persist. Develop solutions to problems with unknown causes where precedents do not exist by applying logic and inference with creativity and initiative. Provide cross-functional support and maintenance for responsible business/technical areas. Additional Information: The candidate should have a minimum of 7.5 years of experience in SAP Sales and Distribution (SD) This position is based at our Hyderabad office A 15 years full-time education is required Qualifications 15 years full time education

About The Role Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited toSystem Verilog, Python/Perl/Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

POSITION SUMMARY & KEY AREAS OF RESPONSIBILITY: This position requires technical leadership and considerable experience in the application of software engineering practices, principles, methods, and techniques. Expected to stay current with technologies and to learn new technologies, processes, and trends. Expected to seek a greater understanding of the business, and business processes, disseminate knowledge to team members, form best practices. Design and Develops high quality software which meets requirements, promote re-use of software components and facilitates ease of support, possess good understanding of design patterns. Analyse, design and implement software mechanisms to improve code stability, performance, and reusability. Participate in and lead code review sessions. Practice Agile development and become familiar with Continuous Improvement, Six Sigma Lean principles, and the Scaled Agile Framework. Assist others in estimating task effort and dependencies, responsible for team commitments within the Sprint. Pro-actively identify and implement process, best practices and tools improvements to improve quality and performance. Provide input and technical content for customer facing documentation, user help materials and customer training. Required to be a source of innovative ideas not only for products but also processes affecting the development projects and personnel. Works within the key business process framework; Defines and provides functional descriptions of new products, processes, and concepts. Have a strong desire for quality, and an attention to detail; excellent analytical skills. Ability to multi-task and prioritize in a fast-paced environment. Ability to work effectively in a team environment composed of peers and cross-functional members Judgment skills needed to assess high-risk areas of a system problem, on which to focus efforts. Work independently with limited supervision. Solid troubleshooting & problem-solving skills involving complex systems. Strong aptitude for learning quickly Provide mentorship to other team members BASIC QUALIFICATIONS: Bachelors Degree in a technical discipline 7-11 years of related experience REQUIRED SKILLS: Excellent knowledge in C#.NET application development and support. Excellent understanding of Test Automation frameworks (NUnit, Rhino, Moq) Strong object-oriented programming skills (C#) Strong understanding of Secure Development Lifecycles Good understanding of Continuous Integration and Delivery practices Good understanding of Windows Experience in working with large teams in SAFe/Agile methodologies Excellent written and verbal communication skills (English) Excellent teamwork and collaboration skills Confident in making design decisions Mentoring less experienced team members Beneficial skills: Domain knowledge of ATM client software and/or transaction processing ISO20022 knowledge Experience with tools utilized in development environment: o Jira o Confluence o Sonar o Github Build and Deployment Pipeline technologies

We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects. About the Role : You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs. What You'll Do : - Design and implement advanced System Verilog/UVM verification infrastructures - Lead verification planning and execution for complex ASIC projects - Develop comprehensive test strategies ensuring thorough design validation - Drive debug resolution through collaboration with cross-functional teams - Mentor and provide technical guidance to verification team members - Enhance and optimize verification methodologies - Own end-to-end SOC verification environments Required Skills & Experience : - BS/MS in Electrical/Computer Engineering - 2+ years of hands-on ASIC verification experience - Expert-level SystemVerilog, UVM, and object-oriented programming skills - Strong proficiency with industry tools like VCS, Xcelium, QuestaSim - Advanced debugging and problem-solving capabilities - Excellent communication and collaboration abilities - CLP and GLS - Python/Perl scripting expertise Nice to Have : - Experience with PCIe, DDR, USB, C2C - Knowledge of on-chip interconnects and processor subsystems - Background in formal verification methods - Prior experience on Emulators

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : Dassault Systemes ENOVIA V5 Good to have skills : NA Minimum 3 year(s) of experience is required Educational Qualification : BE/BTech or Equivalent Project Role :Application Developer Project Role Description :Design, build and configure applications to meet business process and application requirements. Must have Skills :Dassault Systemes ENOVIA V5Good to Have Skills : No Technology SpecializationJob Requirements :Key Responsibilities :1 Able to work independently in development / customization of CATIA v5 using CAA 2 Work closely with the Team Lead to understand the requirements and assist them with requirements definition and refinement 3 Should be able to understand design, do development, and analysis and delivery of the requirements Technical Experience :1 3 to 5 years of experience in Catia v5 customization Projects2 CATIA customization using CAA 3 Good Functional Knowledge on CATIA V54 Good skills in C and Objected oriented programming Professional Attributes :1 Should have good analytical and communication skills 2 Should be willing to work in shifts 3 Should be a good team player Educational Qualification:BE/BTech or EquivalentAdditional Info : Qualifications BE/BTech or Equivalent

About The Role RTL design for 3D Graphics Fixed Function components. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration of the GPU block. Must Have Skills IP RTL design, graphics domain, GPU RTL, micro-architecture, system verilog, AI will be a plus. Qualifications You must possess a minimum of bachelor's degree / MS degree in Computer Engineering, Computer Science or Electrical Engineering with 8+ years of industry experience. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

Greetings From Dexcel Designs! We are inviting applications for FPGA Design and Verification Engineer Job Overview: We are seeking FPGA Design and Verification Engineers with 3-6 years of experience in RTL design, FPGA verification, and high-speed interface development . This role involves designing, implementing, and validating FPGA-based systems while working closely with cross-functional teams in hardware and embedded software development. Key Responsibilities: Develop and implement RTL designs for FPGA-based systems. Perform functional verification and validation of FPGA designs. Work on timing analysis, synthesis, and debugging of FPGA architectures. Collaborate with hardware, embedded software, and system architects to ensure seamless integration. Debug FPGA designs using industry-standard tools and methodologies . Technical Skills Required: Strong understanding of RTL design (Verilog/VHDL) and FPGA implementation. Experience with FPGA tools such as Vivado, Quartus, Synplify, ModelSim, and QuestaSim . Hands-on experience with at least one of the following high-speed interfaces : PCIe, SATA, USB, DisplayPort, JESD204B, SRIO MII/RMII/GMII/RGMII/SGMII/XAUI/RXAUI DDR/LPDDR/DDR2/DDR3, QDR memories Knowledge of FPGA debugging techniques, timing closure, and constraint handling . Preferred Skills: Experience in FPGA-based hardware design and testing . Exposure to SoC architectures and system-level integration . GFPGA Design and Verification Engineer ) and power integrity (PI) analysis .G

Job Description: Be a member of the team that plays a significant role in ensuring the quality of next generation processors for Smart phones and Smart card through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include Interfacing with the design teams to ensure DFT design rules and guidelines are met. Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques. MBIST verification and test pattern generation through Mentor tool. Work closely with design team on IDDQ constrains validation and pattern generation along with IVA analysis. Simulating and verifying the ATPG (SAF, TDF) and MBIST patterns on unit delay and min/max timing corners. Working with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE debug. Lead team of 2-3 engineers working bin DFT/ADFT pattern generation and validation Contribute to technical innovation, development of innovative techniques in the area of test cost reduction, simulation time reduction and quality enhancement Responsible for supporting post Si debug effort, issue resolution Developing, enhancing and maintaining scripts as necessary. Skills: Minimum of 8 -12 year experience in ASIC/DFT and various aspects simulation, Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug In depth knowledge and hands on experience in ATPG, coverage analysis, Transition delay test coverage analysis. In-depth knowledge and hands on experience in Silicon debug, yield optimization Expertise in test mode timing constraints definition, Hands on experience with prime time is an added advantage Expertise in scripting languages such as perl, shell, etc. is an added advantage Knowledge/experience in post Si debug support Experience in simulating test vectors Working experience in System Verilog, Vera, modelsim tools Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking work on several high priority designs in parallel. Past experience or ability to manage team Excellent problem solving skills Excellent communication and team work skills Experience with test tools such as Tetramax, Logic vision, Modelsim is highly desirable.

Junior ASIC Verification Engineer Who we are Kinara is a Bay Area-based venture backed company Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof Mark Horowitz (http://www-vlsi stanford edu/~horowitz/) and Prof Christos Kozyrakis (http://csl stanford edu/~christos/) What we do Our game-changing AI solutions revolutionize what people and businesses can achieve Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it About The Role We are seeking a talented junior ASIC Verification Engineer to join our dynamic team The successful candidate will be responsible for leading and executing verification efforts for complex ASIC designs, ensuring the quality and reliability of our products This is what you are responsible for Develop and maintain verification plans, testbenches, and test cases for ASIC designs Design and implement SystemVerilog/UVM-based verification environments Create and execute test cases to verify functionality, performance, and compliance with specifications Write testplans, testcases at unit or SOC level Necessary Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field expertise in SystemVerilog, C, C++ languages Experience with verification tools such as VCS, QuestaSim, or similar is helpful Excellent problem-solving and debugging skills Strong communication and teamwork abilities Preferred Qualifications Experience with scripting languages such as Python or Perl Programming languages such as C,C++ Knowledge of industry standards and protocols (e g , AXI, AHB, etc) Familiarity with formal verification techniques Work culture We at Kinara have an environment that fosters innovation Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges We share responsibilities in everything we do, where every point of view is valued Join us! Now tell us your story We are looking forward to reviewing your application Make your mark!

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. General Summary: We are hiring talented engineers for CPU RTL Power targeted for high performance, low power devices. In this role, you will be responsible for all key aspects of CPU power modeling and analysis, and RTL power estimation and optimization of high-performance energy efficient CPU designs. Required qualifications — BS degree in Electrical or Computer Engineering with 15+ years of CPU RTL power modeling and estimation experience. — Deep understanding of CPU or ASIC low power design including expertise in active and Idle power optimization, RTL clock gating techniques, CPU power modeling and analysis for power/performance tradeoffs and battery life projections — Working knowledge of Verilog and/or VHDL with hands-on experience in low-power simulation tools such as PowerArtist and PTPX. — Knowledge of logic design principles along with power and timing implications. Preferred qualifications — MS degree in Computer or Electrical Engineering with at least 3 years of practical experience — Very good understanding of low power minimization techniques — Experience using a scripting language such as Perl or Python — Strong problem solving, organizational and communication skills, and ability to work in a fast-paced and dynamic environment Roles and Responsibilities As an RTL Power engineer you will own and/or participate in the following tasks: — Estimate/analyze RTL power for CPU modules (using PowerArtist or equivalent tool) and optimize power at various stages of the design to meet targets working with architecture, RTL, verification and physical design teams — Create comprehensive CPU power models, identify early power targets and achieve correlation with physical design, and analyze power/performance/area tradeoffs — Build scripts (using Python/Perl) to automate power estimation/analysis flow and create algorithms to analyze complex HW throttling mechanisms to achieve peak CPU performance within EDP, TDP and peak current limits Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In the role of GPU Functional Verification Engineer, your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools "“ working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools "“ both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: n the role of GPU Functional Verification Engineer, your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools "“ working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools "“ both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a "CPU Core Validation Engineer" you would be part of CPU Validation team in CPU org working on validation of CPU core pipeline arch and micro arch features. Roles and Responsibilities: Develop detailed test plan considering the IP arch and uarch features. Work with CPU design and verification teams to develop CPU bring up and functional validation test plans for the IP owned. Develop validation methodology and test contents to exercise on emulators during pre-Si phase and on Silicon. Work with SOC bring up teams, software teams to plan CPU core features bringup and end to end validation. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist validation of CPU on silicon. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future CPU bringup"™s. Minimum Requirements: BA/BS degree in CS/EE with 5+ years"™ experience. 5+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools. Preferred Requirements: Good understanding of micro-processor architecture, in domains such as:Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management. Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness. Experience in writing Test plans and Assembly code. Ability to develop and work independently on a block/unit of the design Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Exp : 3 "“ 5 Yrs Position : Senior or Lead Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The role generally entails a mixture of: Ownership of a piece of the test bench Planning & execution of feature additions and mode re-enablement on particular variants Bug fixes Debug of regression signatures Developing/Deploying new tools for performance validation Performance monitor and profiler development and deployment Workload specific simulations on the emulator Following skillset is required: Strong Python, C++ skills Reading Specs and developing test plans Monitors, scoreboards, sequencers, and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening 6 months - 1 Year of industry experiences in the following areas:- Basic of digital design concepts, fifo etc Basic understanding of DDR is a plus Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering Candidate must possess right analytical skills, debug oriented mindset and must be open to discuss , deep dive, collate and present the design and environment understanding . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5-7 years of experience in SOC Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication.