Senior Physical Design Engineer Truechip

5.0 - 10.0 years

0 Lacs

hyderabad, telangana, india

On-site

Senior Physical Design Engineer Physical Design >> Senior Physical Design Engineer Post Senior Physical Design Engineer Required Experience 5 to 10 Years Location: Delhi NCR, Bangalore, Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Physical Design Engineer knowledge of PD Flow from netlist to GDS (Floorplanning, Synthesis, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI) Good idea about OCV/MMMC and multi power designs (Level shifters, Isolation cells etc) Should have worked extensively on XTalk/SI/EM Knowledge about CTS, Clock tree methodology and clock skewing. Tool specific knowledge: ICC, innovus, primetim...

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Static Timing Analysis Infogrowth

7.0 - 10.0 years

35 - 40 Lacs

bengaluru

Work from Office

SDC and constraints syntax Timing signoff tools like Primetime / Tempus is a must MMMC, DMSA or Tweaker Block /SOC,AOCV/POCV, TCL / Perl.

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STA lead Techno Facts Solutions

7.0 - 12.0 years

30 - 45 Lacs

bengaluru

Work from Office

Role & responsibilities Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. • Own SDC constraint generation, validation, and refinement at top-level. • Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure. • Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations. • Conduct MMMC (Multi-Mode, Multi-Corner) timing analysis, including OCV, AOCV, and POCV variations. • Integrate timing reports from multiple blocks, perform hierarchical timing closure, and ensure sign-off compliance. • Work with DFT teams to analyze scan shift and at-speed test ...

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Sta Engineer Giga-ops Global Solutions

8.0 - 13.0 years

12 - 24 Lacs

bengaluru

Work from Office

Job Role: * Collaborate with cross-functional team on timing closure. * Perform STA using TCL and MMMC tools. * Ensure compliance with industry standards during static timing analysis. Mail: chaitanya.vasamsetti@gigaopsglobal.com Contact: 7729881999 Office cab/shuttle Food allowance Health insurance Annual bonus Provident fund

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STA lead Xanika Infotech

8.0 - 11.0 years

25 - 30 Lacs

bengaluru

Work from Office

Role & responsibilities We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimiza...

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STA Lead Team Computers

5.0 - 8.0 years

25 - 40 Lacs

bengaluru

Work from Office

We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations. Conduct MMMC (Mul...

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