8.0 - 13.0 years

12 - 24 Lacs

bengaluru

Work from Office

Job Role: * Collaborate with cross-functional team on timing closure. * Perform STA using TCL and MMMC tools. * Ensure compliance with industry standards during static timing analysis. Mail: chaitanya.vasamsetti@gigaopsglobal.com Contact: 7729881999 Office cab/shuttle Food allowance Health insurance Annual bonus Provident fund

Posted 1 week ago

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STA lead Xanika Infotech

8.0 - 11.0 years

25 - 30 Lacs

bengaluru

Work from Office

Role & responsibilities We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations. Conduct MMMC (Multi-Mode, Multi-Corner) timing analysis, including OCV, AOCV, and POCV variations. Integrate timing reports from multiple blocks, perform hierarchical timing closure, and ensure sign-off compliance. Work with DFT teams to analyze scan shift and at-speed test timing . Automate report generation, violation tracking, and closure metrics using Tcl, Perl, or Python . Provide guidance on timing budgets for IP/block owners. Interface with foundries and EDA vendors to resolve tool and library issues.

Posted Date not available

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STA Lead Team Computers

5.0 - 8.0 years

25 - 40 Lacs

bengaluru

Work from Office

We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes. Key Responsibilities: Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners. Own SDC constraint generation, validation, and refinement at top-level. Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure . Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations. Conduct MMMC (Multi-Mode, Multi-Corner) timing analysis, including OCV, AOCV, and POCV variations. Integrate timing reports from multiple blocks, perform hierarchical timing closure, and ensure sign-off compliance. Work with DFT teams to analyze scan shift and at-speed test timing . Automate report generation, violation tracking, and closure metrics using Tcl, Perl, or Python . Provide guidance on timing budgets for IP/block owners. Interface with foundries and EDA vendors to resolve tool and library issues.

Posted Date not available

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