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3.0 - 8.0 years
5 - 15 Lacs
bengaluru
Hybrid
Years: 3yrs to 8yrs Location: Bangalore JD: 3-8 years of experience in Memory/Custom Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Good Knowledge in EM and IR run and fix. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Please share updated resume to madhuri.a.sivaraju@capgemini.com
Posted 2 months ago
8.0 - 13.0 years
10 - 20 Lacs
noida
Work from Office
8+ years of experience in Memory/Custom Layout design. Memory Leafcell layout library design from scratch Knowledge on different types of memory architectures. Knowledge in optimized layout design for better performance. Knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug Proficient in Cadence Virtuoso layout editor and Calibre Interested can contact me at shubhanshi@incise.in
Posted 3 months ago
3 - 5 years
20 - 35 Lacs
Bengaluru
Work from Office
Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow
Posted 7 months ago
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