RTL Engineer/ RTL Lead and above Tessolve

5.0 - 20.0 years

0 Lacs

karnataka

On-site

You have an exciting opportunity with Tessolve Semiconductor in Bangalore for the roles of RTL Design Engineer and Design Verification Engineer. For the position of RTL ASIC Engineer, you should have at least 7 years of work experience in ASIC/IP Design with expertise in Logic design and RTL design. Your responsibilities will involve IP design and integration, along with proficiency in tools such as Lint and CDC for ASIC development. Knowledge of Synthesis and understanding of timing concepts would be advantageous. Additionally, familiarity with AMBA protocols like AXI, AHB, APB, and SoC clocking/reset architecture is preferred. As a Design Verification Engineer, you are required to have 5 to 20 years of experience. You should be well-versed in IP verification using SV/UVM, SOC Verification using C/SV, and Third Party VIP Integration. Your expertise in Interconnect Protocols such as AHB, AXI, APB, SOC Interfaces like GPIO, SPI, I2C, UART, High-Speed Serial Interfaces including PCIe Gen 3/4, USB, MIPI, and Memory Interfaces like DDR or HBM I/O will be crucial. Proficiency in Coverage Closure (Code, Functional, Toggle) and tools like Synopsys VCS or Cadence Incsive is essential. Experience in Technical Documentation, Foundry Porting, and Technology Library Conversion related to Verification will be advantageous. If you meet the requirements and are interested in these positions, please share your updated CV with Gayatri Kushe at gayatri.kushe@tessolve.com or contact at 6361542656. Thank you for considering this opportunity with Tessolve Semiconductor.,

Posted 1 week ago

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