Lead Memory Design Engineer : Noida Incise Infotech

8.0 - 13.0 years

10 - 20 Lacs

noida

Work from Office

Candidate should have worked in memory domain and preferably candidate should have worked on Memory characterization, design and validation. Candidate should be familiar with layout parasitic extraction and challenges in deep submicron technologies. Candidates should be familiar with Spice decks and should be able to write spice decks, stimulus and test vectors and validate them. Candidates should have good knowledge and should have hands on experience with fast simulator tools. Candidate should have good memory design knowledge and should have debugging skills and should be familiar with waveform viewers etc . Candidate should be familiar with NMDL + CCST. libs and should have hands on experience on generating libs and sign off QA checks etc . Candidate should be familiar with validating libs with tight stimulus (sanity) runs. Candidates with scripting knowledge will be preferred Interested can contact me at shubhanshi@incise.in

Posted 6 days ago

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Lead Memory Design Engineer ACL Digital

6.0 - 10.0 years

0 Lacs

karnataka

On-site

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout activities, ensuring designs meet requirements for DFM and reliability, contributing to methodology development, supporting silicon bring-up, and providing technical leadership to junior engineers. To be successful in this role, you should have a B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering, along with 8+ years of experience in full-custom memory design. You should possess a solid understanding of CMOS analog/digital circuit design principles, expertise in circuit simulation tools, experience with advanced nodes, and hands-on experience with variation analysis, IR drop, and EM checks. Strong analytical, communication, and leadership skills are essential for this position. Preferred qualifications include experience in memory compiler design, knowledge of low-power memory design techniques, experience with ECC and redundancy strategies, familiarity with ISO 26262/Safety compliance, and scripting knowledge for automation of design and simulation flows. If you are interested in this opportunity, please share your CV with Sharmila.b@acldigital.com.,

Posted 1 month ago

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