3.0 - 7.0 years

7 - 11 Lacs

bengaluru

Work from Office

About MIPS MIPS is a leader in high-performance RISC-V CPU IP, enabling innovation across automotive, AI, data center, and embedded markets Our engineering teams are building the next generation of compute solutions, and we are looking for passionate talent to join us in shaping the future of semiconductors, Position Overview We are seeking an experienced Lead DFT Engineer to drive the architecture, implementation, and validation of Design for Test (DFT) solutions across complex SoCs This role requires deep technical expertise in DFT flows, strong leadership skills, and proven ability to deliver high-quality, low-cost, and low-power test strategies for production silicon, Key Responsibilities Define and deploy DFT architecture for SoCs, including scan, ATPG, memory BIST, boundary scan, and analog test solutions, Lead project-level DFT execution: schedule planning, task assignment, milestone tracking, and status reporting, Drive pre-silicon verification of DFT IPs, including RTL generation, simulation, scan insertion, ATPG bring-up, and coverage analysis, Collaborate with EDA vendors to optimize simulation and verification flows for DFT, Partner with Test and Product Engineering teams for silicon bring-up, debug, and production test optimization, Support STA constraints development and AMS verification for analog IP trims and characterization, Mentor and ramp up junior engineers through training and technical guidance, Contribute to automation, innovation, and continuous improvement of DFT methodologies, Qualifications Tech Tech 7+ years of hands-on DFT experience, including SoC-level ownership, Strong expertise in ATPG, scan insertion, memory BIST, STA, and analog, AMS test flows, Proven track record of silicon bring-up and post-silicon debug, Experience with DFT tools such as Cadence Genus, Modus, Xcelium, JasperGold, or similar, Proficiency in SystemVerilog, VHDL and scripting languages (Python, Perl, Tcl, C), Strong problem-solving skills, analytical mindset, and ability to lead cross-functional initiatives, Preferred Skills Prior experience driving low-power and cost-sensitive DFT architectures, Contributions to patents, publications, or conference presentations in DFT, test, Ability to work in a fast-paced environment with global teams, Strong communication and leadership skills with a hands-on approach, Why Join MIPS Be part of a team driving innovation in RISC-V CPU IP and SoC development, Work on cutting-edge semiconductor designs with global impact, Collaborative, growth-focused environment with opportunities for innovation and leadership,

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