Staff Engineer, ASIC Development Engineering (DFT) Western Digital

4.0 - 8.0 years

0 Lacs

karnataka

On-site

As part of the ASIC modeling team, you will be responsible for developing, maintaining, and testing the NAND/SoC models using C/C++/SystemC. The SoC models aim to accurately capture the functionality of the controller chip that oversees the NAND storage. You should have 4 to 7 years of experience and possess expertise in DFT implementation and verification. Additionally, experience in MBIST implementation and verification, along with a strong grasp of DFT/MBIST fundamentals, is essential. You will be involved in tasks such as DRC Clean up, coverage improvement, and modifying MBIST algorithms. It would be beneficial to have knowledge in PERL/TCL Scripting/Python and using assertions for monitoring clock frequencies and test-related registers. Familiarity with yield analysis and improvement flow, understanding CLP constructs, and working in multi-voltage, multi-power design environments will be advantageous. Your expected roles will include architecting DFT based on the PETE, Design, and Customer specifications. A self-motivated, self-driven attitude with a thirst for learning is desirable for this position. The ideal candidate should hold a BE/Btech/Mtech/ME degree. Western Digital values diversity and believes that embracing various perspectives leads to the best outcomes. The company is dedicated to creating an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution. Western Digital is committed to providing equal opportunities to applicants with disabilities. If you require accommodations during the application process, please contact us at staffingsupport@wdc.com with details of your request, including the job title and requisition number.,

Posted 1 month ago

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DFT (Design For Test) Engineer Deori Recruiterhub Solutions (opc)

7.0 - 12.0 years

6 - 10 Lacs

Hyderabad, Pune, Bengaluru

Work from Office

Qualification : Bachelors in Computer Science / Electronics / Electrical Engineering Key Responsibilities: Collaborate with ASIC design teams to ensure DFT rules and coverage are metGenerate high-quality ATPG patterns for SAF/TDF using on-chip test compression Work on MBIST verification and repair using tools like Mentor Run ATPG & MBIST verification using unit delay and min/max corner simulations Deliver manufacturing test patterns for ATE in collaboration with product/test teamsSupport post-silicon debug and issue resolution Develop diagnostic tools for ATPG, MBIST, and ATE bring-upEnhance and maintain scripting for DFT flows Preferred Experience & Skills:Hands-on experience with Full Chip DFT and Silicon Validation Strong understanding of DFT concepts, ATPG coverage, yield enhancement, and silicon debug Proficient in Memory test & failure analysis Tool knowledge: ATPG TestKompress MBIST MentorETVerify Simulation VCS (preferred), ModelSim Scripting in Perl, Shell is a plus Comfortable working in international teams with strong communication skills Ability to multitask and work on high-priority designs in parallel Quick learner, adaptable to new tools and methodologies Location : Bangalore | Hyderabad | Cochin | Pune

Posted 2 months ago

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