DFT (Design For Test) Engineer Deori Recruiterhub Solutions (opc)

7.0 - 12.0 years

6 - 10 Lacs

Hyderabad, Pune, Bengaluru

Work from Office

Qualification : Bachelors in Computer Science / Electronics / Electrical Engineering Key Responsibilities: Collaborate with ASIC design teams to ensure DFT rules and coverage are metGenerate high-quality ATPG patterns for SAF/TDF using on-chip test compression Work on MBIST verification and repair using tools like Mentor Run ATPG & MBIST verification using unit delay and min/max corner simulations Deliver manufacturing test patterns for ATE in collaboration with product/test teamsSupport post-silicon debug and issue resolution Develop diagnostic tools for ATPG, MBIST, and ATE bring-upEnhance and maintain scripting for DFT flows Preferred Experience & Skills:Hands-on experience with Full Chip DFT and Silicon Validation Strong understanding of DFT concepts, ATPG coverage, yield enhancement, and silicon debug Proficient in Memory test & failure analysis Tool knowledge: ATPG TestKompress MBIST MentorETVerify Simulation VCS (preferred), ModelSim Scripting in Perl, Shell is a plus Comfortable working in international teams with strong communication skills Ability to multitask and work on high-priority designs in parallel Quick learner, adaptable to new tools and methodologies Location : Bangalore | Hyderabad | Cochin | Pune

Posted 21 hours ago

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