5 Mask Design Jobs

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be able to perform standard cell layout development and physical verification activities for complex designs as per provided specifications. Should have expertise in layout area and routing optimization, design rules, yield and reliability issues. Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. Should have adequate knowledge of schematics, interface with circuit designer and CAD team. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., Excellent in problem-solving skills in solving area, power, performance, and physical verification of custom layout. Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Caliber- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques. Should have leadership qualities and able to do multi-tasking as required. Should be able to work in a team environment and able to guide and provide technical support to the fellow team members. Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills. Knowledge of Skill coding and layout automation is a plus. mandatory skillset: stdcells layout || cadence virtuoso || physical verifications checks

Job Description: Role and Responsibilities: Develops and prepares stdcells layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. Check design layouts and detailed drawings. 3-5 years of experience. Qualification/Requirements: Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be able to perform standard cell layout development and physical verification activities for complex designs as per provided specifications. Should have expertise in layout area and routing optimization, design rules, yield and reliability issues. Good understanding of layout fundamentals i.e., Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. Should have adequate knowledge of schematics, interface with circuit designer and CAD team. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., Excellent in problem-solving skills in solving area, power, performance, and physical verification of custom layout. Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Caliber- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques. Should have leadership qualities and able to do multi-tasking as required. Should be able to work in a team environment and able to guide and provide technical support to the fellow team members. Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills. Knowledge of Skill coding and layout automation is a plus. mandatory skillset: stdcells layout || cadence virtuoso || physical verifications checks

We are seeking a highly skilled and motivated Analog Layout Leader to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of Analog IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore Work Expertise : 5 Years 12 Years DESIRED PROFILE : Expertise in working with large analog layout teams Expertise working on high-performance cores Expertise in working on planar and finfet technology nodes Expertise in executing the mixed signal layout, lvs / drc /antenna checks on complex custom analog/RF mixed-signal integrated circuits. Expertise in working with circuit designers and CAD engineers to perform custom analog mixed signal blocks layout Expertise in custom layout design techniques, CAD methodologies and process flows Expertise in Transistor level floorplan in a multi-voltage, mixed-signal, high speed and noise-sensitive environment Expertise in analog layout techniques like Device matching, shielding, LOD/STI, WPE, PSE, OSE, RF Concepts, minimizing parasitics and highpower routing JOB SPECS : Responsible to perform IC mask layout design and physical verification of Custom analog / RF mixed signal, IO & ESD designs and Block/Module level Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire, build technical teams from scratch and manage high caliber technical teams across GCC, ODC and onsite. Must be willing to work at customer sites as per customer needs Must be willing to travel worldwide at short notice as per customer needs Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Specs : We are seeking a highly skilled and motivated Analog Circuit Designer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of Analog / Mixed Signal IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C with 4+ Years of work expertise in mixed-signal or CMOS circuit design Expertise in analog blocks like power management DC-DC convertor, LDOs or Expertise in designing ADC / DAC/ PLLs or Experience in simulation or characterization of IO cells Design and architect CMOS analog and mixed-signal integrated circuits Simulate designs with state-of-the-art CAD tools Document designs and simulation results Experience with high-speed SERDES circuits Knowledge of layout issues Experience with circuit simulators (HSPICE, Spectre, etc) Experience with Cadence Design Environment is an asset Working knowledge of PERL and UNIX shell scripting languages is an asset Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. NOTE : Preferred resources holding valid regional work permits only Location : Moscow, USA,Bengaluru,Hubli,Kolkata

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node 180 nm is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Taiwan, Vietnam