3 Lvsdrc Checks Jobs

As an Analog Layout Engineer, you will be responsible for designing and implementing analog layout solutions. With 3 to 7 years of experience, you will be based in Ranchi, Jharkhand. Your key skills should include proficiency in LVS/DRC checks and EDA tools, along with experience in lower technology nodes. A strong understanding of layout analysis, floor planning, and matching techniques is essential for this role. This is a full-time, permanent position with the interview mode being virtual and in-person. The ideal candidate should be able to join immediately or within 45 days. Immediate joiners are preferred, and the budget for this position is open based on the candidate's skills and experience.,

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and integrating them into full-chip designs. Your expertise in lower technology nodes, physical layout techniques, and verification processes will be crucial for success in this role. You will collaborate with circuit design teams to optimize layout quality and performance, ensuring that layouts meet design matching and parasitic constraints. Working with advanced nodes like 7nm, 16nm, and 28nm, you will play a key role in advancing the company's cutting-edge projects. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate with circuit design teams to optimize layout quality and performance - Ensure layouts meet design matching and parasitic constraints - Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: - 3+ years of relevant Analog Layout experience - Proficiency in LVS/DRC checks and EDA tools - Experience with lower technology nodes (3nm, 5nm, 7nm, 10nm, 16nm, 28nm, etc.) - Good understanding of layout matching, parasitic extraction, and floor planning - Strong verbal and written communication skills - Ability to work independently and within cross-functional teams In this role, you will be a Circuit Design Engineer at ARF Design, working on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. You will derive circuit block-level specifications from top-level specifications and perform optimized transistor-level design of analog and custom digital blocks. Running SPICE simulations to meet detailed specifications and guiding layout design for best performance, matching, and power delivery will be part of your responsibilities. You will also characterize design performance across PVT + mismatch corners and conduct design reviews at various phases/maturity of the design. Qualifications: - BE/M-Tech in Electrical & Electronics - Strong fundamentals in RLC circuits, CMOS devices, and digital design concepts (e.g., counters, FSMs) - Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators - Collaborative mindset with a positive attitude If you have 3+ years of experience and possess the required skills, please share your updated resume [Name_Post_Exp] to divyas@arf-desgn.com. This is a full-time, permanent position located in person at Bhubaneswar and Ranchi.,

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and full-chip integration. Your role will involve performing and resolving LVS/DRC violations independently, collaborating with circuit design teams to optimize layout quality and performance, and ensuring layouts meet design matching and parasitic constraints. You will have the opportunity to work with advanced nodes like 7nm, 16nm, and 28nm, leveraging your 3+ years of relevant Analog Layout experience. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate with circuit design teams to optimize layout quality and performance - Ensure layouts meet design matching and parasitic constraints - Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: - 3+ yrs of relevant Analog Layout experience - Proficiency in LVS/DRC checks and EDA tools - Experience with lower technology nodes (3nm, 5nm, 7nm, 10nm, 16nm / 28nm ETC) - Good understanding of layout matching, parasitic extraction, and floor planning - Strong verbal and written communication skills - Ability to work independently and within cross-functional teams In this role, you will be a Circuit Design Engineer at ARF Design, where you will be working on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. Your responsibilities will include deriving circuit block level specifications from top-level specifications, performing optimized transistor-level design of analog and custom digital blocks, running SPICE simulations to meet detailed specifications, and guiding layout design for best performance, matching, and power delivery. Key Responsibilities: - Derive circuit block level specifications from top-level specifications - Perform optimized transistor-level design of analog and custom digital blocks - Run SPICE simulations to meet detailed specifications - Guide layout design for best performance, matching, and power delivery - Characterize design performance across PVT + mismatch corners and reliability checks (aging, EM, IR) - Generate and deliver behavioral (Verilog), timing (LIB), and physical (LEF) models of circuits - Conduct design reviews at various phases/maturity of the design Qualifications: - BE/M-Tech in Electrical & Electronics - Strong fundamentals in RLC circuits, CMOS devices, and digital design concepts (e.g., counters, FSMs) - Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators - Collaborative mindset with a positive attitude If you have 3+ years of experience and are interested in these exciting opportunities, please share your updated resume [Name_Post_Exp] to divyas@arf-desgn.com. Join ARF Design for a chance to work on advanced nodes with fast-track interview and onboarding processes.,