703 Lvs Jobs - Page 9

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s na...

Your role at Micron Technology will involve designing and maintaining standard cells layout for new DRAM products on new technology. You will lead stdcells layout projects from initial specification definition until PPA qualified library release. Collaborating closely with the DTCO team, you will develop stdcells architecture for emerging technologies. Additionally, you will be responsible for performing layout verification tasks such as LVS/DRC/Latchup, quality checks, and documentation. Ensuring on-time delivery of block-level layouts with acceptable quality will be a key part of your responsibilities. Demonstrating leadership skills in planning, area/time estimation, scheduling, delegatio...

You should have a minimum of 5 years of experience as an analog layouter and be familiar with GF40nm node technology. Your expertise should include working with PVS, LVS, DRC, Antenna, and MRC tools. Additionally, you should have a proven track record of delivering IP top-level for chip-level integration and conducting thorough reviews and sign-offs. Experience in coordinating the work of other layouters at the sub-IP level would be advantageous.,

Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo One, a fully autonomous ride-hailing service, and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over one million rider-only trips, enabled by its experience autonomously driving tens of millions of miles on public roads and tens of billions in simulation across 13+ ...

Job Description: We are actively hiring Analog Layout Engineers with 3 to 6 years of industry experience. Ideal candidates must have solid expertise in lower technology nodes, physical layout techniques, and verification processes. ARF provides an excellent platform to work on advanced nodes with fast-track interview and onboarding processes. Key Responsibilities: ● Design and development of analog layout IP blocks and full-chip integration ● Perform and resolve LVS/DRC violations independently ● Collaborate with circuit design teams to optimize layout quality and performance ● Ensure layouts meet design matching and parasitic constraints ● Work with advanced nodes like 7nm, 16nm, and 28nm R...

About Tata Electronics: Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence. Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term s...

Job Description: We are actively hiring Analog Layout Engineers with 3 to 6 years of industry experience. Ideal candidates must have solid expertise in lower technology nodes, physical layout techniques, and verification processes. ARF provides an excellent platform to work on advanced nodes with fast-track interview and onboarding processes. Key Responsibilities: ● Design and development of analog layout IP blocks and full-chip integration ● Perform and resolve LVS/DRC violations independently ● Collaborate with circuit design teams to optimize layout quality and performance ● Ensure layouts meet design matching and parasitic constraints ● Work with advanced nodes like 7nm, 16nm, and 28nm R...

Job Information Job Opening ID ZR_158_JOB Industry Semiconductor Date Opened 08/14/2025 Job Type Full time Work Experience 4 -7 years City Bangalore State/Province Karnataka Country India Zip/Postal Code 560078 Job Description Job Summary: We are looking for an Engineer with good attitude who seeks new challenges and has good analytical and communication skills. A Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing layout of digital circuits DRC, LVS and other Physical verification checks Design Floor-plan, Routing Crosstalk Fixes Electro-migration fixes IR Fixes Handling different tools: Calibre, Virtuoso PREFE...

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well...

Job Title: EDA Tool & CAD Engineer Location: Hyderabad / Bangalore / Hybrid / Remote Department: Semiconductor / VLSI CAD & EDA Infrastructure Employment Type: Full-Time Job Summary We are seeking an experienced EDA Tool & CAD Engineer to develop, maintain, and optimize the design automation infrastructure supporting our semiconductor design teams. This role is critical for ensuring that RTL, verification, physical design, DFT, and AMS teams have efficient, reliable, and well-integrated tool flows for chip development from front-end to tape-out. Key Responsibilities ● Install, configure, and maintain EDA tools across the chip design flow (RTL, verification, synthesis, PnR, STA, DFT, LVS/DRC,...

Alternate Job Titles: Senior CAD Engineer Senior Physical Verification Engineer Senior EDA Tool Developer Senior Design Enablement Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an enthusiastic and forward-thinking engineer who thrives in dynamic, multicultural environments and is passionate about pushing the ...

Category Engineering Hire Type Employee Job ID 12479 Remote Eligible No Date Posted 11/08/2025 Alternate Job Titles: Senior CAD Engineer Senior Physical Verification Engineer Senior EDA Tool Developer Senior Design Enablement Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an enthusiastic and forward-thinking e...

Hi Folks, Experience : 4+ Yrs Location: Noida Minimum 4 years of experience in Physical Verification * Hands on debugging skills in different physical verification checks like LVS,DRC,ERC,PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools. * Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. * Working experience in cutting edge technologies such as 5nm, 7nm and 16ff process nodes is desire

Alternate Job Titles: Senior CAD Engineer Senior Physical Verification Engineer Senior EDA Tool Developer Senior Design Enablement Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an enthusiastic and forward-thinking engineer who thrives in dynamic, multicultural environments and is passionate about pushing the ...

#Connections #Hiring Hi Connections, We are hiring.... Job Title: Physical Design Engineer (PD) Location: Hyderabad / Bangalore Department: Semiconductor / VLSI Physical Design Employment Type: Full-Time Experience: 3+Years Job Summary: We are seeking a skilled Physical Design Engineer to take ASIC/SoC designs from RTL to GDSII, ensuring optimal performance, power efficiency, and area utilization. The role involves synthesis, floorplanning, placement, routing, timing closure, and physical verification, working closely with RTL, verification, and DFT teams to achieve first-silicon success. Key Responsibilities ● Perform RTL synthesis with timing, area, and power constraints. ● Develop floorpl...

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Lead the layout...

JD: Analog Layout Engineer Experience: 3 to 7 years Location: Ranchi, Jharkhand Required Key Skills: Proficient in LVS/DRC checks and EDA tools. Experience in lower technology nodes. Strong understanding of layout analysis, floor planning, and matching techniques. Employment Type: Full-Time | Permanent Interview Mode : Virtual and In person Notice Period: Immediate to 45 Days Immediate Joiners Preferred Open Budget Based on Skills

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems in order to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. This position is focused on floor-planning expertise at both block and...

You will be integrated into the Foundry IP Development team in Bangalore at GLOBALFOUNDRIES. Collaborating closely with various engineering teams worldwide, you will be responsible for developing layout for Standard Cell IPs to facilitate high-quality product designs based on Globalfoundries" advanced process nodes. Your main responsibilities will include: - Designing layout for Standard Cell IPs - Performing layout checks such as LVS, DRC, DFM, EMIR - Reviewing layouts and assisting other layout teams - Preparing design kits from the layout side, along with verification and validation - Providing support for layout automation and scripting - Taking initiatives for productivity improvements ...

Qualcomm India Private Limited is seeking a Layout Engineer to develop block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. In this role, you will utilize your understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using various tools and techniques to identify and troubleshoot issues, while staying updated on new verification methods. Collaborating with multiple internal and external stakeholders, you will align on projects, provide updates, and resolve issues. The id...

Company Qualcomm India Private Limited Job Area Engineering Services Group, Engineering Services Group > Layout Engineer General Summary Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, an...

Company Qualcomm India Private Limited Job Area Engineering Services Group, Engineering Services Group > Layout Engineer General Summary Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, an...

Company: Qualcomm India Private Limited Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates,...

Your Job The PCB Designer will be responsible for creating and optimizing PCB layouts, ensuring high-quality design for manufacturability, reliability, and performance. This position requires strong knowledge of PCB design principles, proficiency in design software, and a collaborative approach to work effectively with cross-functional teams, including hardware, firmware, signal integrity, and manufacturing. Our Team The PCB Design Engineering Team at Koch Industries is a talented and innovative group dedicated to developing state-of-the-art hardware solutions. We work collaboratively across disciplines to design, prototype, and test high-quality hardware components that support our company'...

Education Requirements B. Tech / M. Tech (ECE) Experience 8 to 20 Years Job Location Hyderabad Shift General (No WFH) Work Week Monday to Friday He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. · Provide technical guidance, mentoring to physical design engrs. · Interf...