423 Lvs Jobs - Page 7

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Ampere is seeking a highly skilled and experienced candidate with proven expertise in PHY hardening, particularly in DDR and SerDes, with a focus on digital implementation and convergence. We are looking for a self-motivated individual with a proven track record in hardening state-of-the-art PHYs and contributing to the development of cutting-edge expertise. What You’ll Achieve As a PHY Hardening Engineer, you will collaborate with architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. This is an exceptional opportunity to showcase your engineering skills in a dynamic, fast-paced environment that fosters innovation and operates at the forefront of technology. High-Speed Digital Design Develop high-speed digital layouts, including DDR and other high-speed interfaces. Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits. Optimize layouts to minimize signal integrity issues, reduce power consumption, and meet timing, power, and manufacturability requirements. Coordinate with PHY vendors for hardening activities and deliverables. Estimate effort and timelines for PHY hardening tasks and provide feedback on timing/PDV. Chip-Level Physical Design Perform chip-level tasks such as floor planning, partitioning, and power/clock distribution. Handle chip assembly and ensure seamless integration of multiple IP blocks into the top-level design. Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC). Collaborate with the packaging team to refine bump placement and package routing considerations. Signal and Power Integrity Familiarity with signal and power integrity concepts in high-performance memory systems. Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation. Perform thermal and power integrity analysis to ensure reliable designs. Knowledge of advanced packaging techniques and considerations, an added plus Design-for-Test (DFT) Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms. Contribute to DFT-based timing closure activities. About You Bachelor's degree & 8 years of related experience or Master's degree & 6 years of related experience Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits Experience developing high-speed digital layouts, including DDR and other high-speed interfaces Handling chip assembly and ensure seamless integration of multiple IP blocks into the top-level design Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC) Worked with architects and RTL teams to develop physical constraints and optimize their design Integrate PHYs, controllers, and memory stacks into the top-level design Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs Handle micro-bump design to ensure proper alignment and minimize resistance Understand the SIPI impacts of bump placement Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms Strong communication and articulation skills are required to excel in this role What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

In this role, you are expected to Develop algorithms in C/C++ for circuit characterization tools critical to develop standard cell libraries. Develop applications using the latest Web technologies (javaScript,AngularJS,HTML) for tool-front end. Have excellent debugging skills Build knowledge of Library characterization Have strong interpersonal skills needed to coordinate deliverables and requirements from several areas within and outside of the organization. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 2-5 years years of soft ware programming experience Strong C/C++programming skills in a Unix/Linux environment are desired. VLSI knowledge, Knowledge in Standard Cell Power Modelling/ Power Domain. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must EDA tool development experience Preferred technical and professional experience Cadence, VLSI knowledge, VHDL/Verilog, computer architecture, Machine Learning/AI.

Job Description Change the world. Love your job. Texas Instruments is seeking a Layout Engineer. In this role, you will develop and prepare multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. You may also check dimensions, write specifications, and verify completed drawings, artwork or digitized plots. Additional job functions may involve checking design layouts and detailed drawings, referring to offline layout leveling charts for details on duties. A bachelor's degree in engineering is typically required. Strong Analog Layout fundamentals and basic Analog design knowledge. Layout Design for various analog circuits like: High Current POWER-FETS, Amplifiers, Comparators, Buffers, BG, Current Mirrors etc. Good floor planning and signal planning skills in Cadence Virtuoso XL Design area and parasitic efficient layouts. Experience in Assura LVS ,DRC verification is an advantage. Good exposure to layout XL utilities like Modgen, Wire assistant etc., Experience in BiCmos technologies is an advantage. Exposure to Digital Place and rout is an advantage. Ability to plan, track, multi-task, Prioritize work to complete the work efficiently . Scripting knowledge in Skill/Perl/Shell/Python is an advantage. Good communication, Team player skills to work with cross functional team and external stakeholders . Good technical documentation and presentations skills. Follow guidelines, processes and checklists for high-quality, on time completion of task. Qualifications Minimum requirements: Minimum education (ie bachelor's degree in electrical engineering) Minimum of 5 years of experience Preferred Qualifications Ability to establish strong relationships with key stakeholders critical to success, both internally and externally Strong verbal and written communication skills Ability to quickly ramp on new systems and processes Demonstrated strong interpersonal, analytical and problem-solving skills Ability to work in teams and collaborate effectively with people in different functions Ability to take the initiative and drive for results Strong time management skills that enable on-time project delivery About Us Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.

90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

Job Title: Physical Design Engineer Company: Wipro Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities: End-to-end ownership of chip-level and block-level floor planning . Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis , DRC/LVS closure , and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required: Strong experience in chip-level and block-level physical design . Hands-on expertise with Innovus and/or Fusion Compiler . Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Interview Process: L1 Technical Round – Virtual L2 Final Round – Virtual Job Types: Full-time, Permanent Pay: ₹3,000,000.00 - ₹7,500,000.00 per year Schedule: Monday to Friday Ability to commute/relocate: Pune, Maharashtra: Reliably commute or planning to relocate before starting work (Preferred) Application Question(s): End-to-end ownership of chip-level and block-level floor planning? Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation? Perform timing analysis, DRC/LVS closure, and physical verification? Work Location: In person

Job Description : Hands on experience in Block level PnR convergence with Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus In this position, candidate is expected to lead all block/chip level PD activities including floor plans, placement, CTS, optimization and routing techniques, RC extraction, STA, EM/IR DROP, PV Familiar with deep sub-micron designs below 10nm preferred BE/B Tech/ME/M TECH

Lead the design, development, and verification of RF and analog IC blocks, including LNAs, mixers, power amplifiers, PLLs, VCOs, and ADC/DACs. Drive system architecture decisions for RF front-end and transceiver designs. Guide and mentor junior engineers, ensuring high-quality design practices. Perform top-level integration, ensuring seamless connectivity and performance of RF, analog, and mixed-signal circuits. Oversee simulation, layout reviews, and post-layout verification, optimizing for performance and manufacturability. Collaborate with layout, test, and product engineering teams for silicon validation and characterization. Define and execute design methodologies for efficiency, robustness, and first-pass success. Work closely with customers and cross-functional teams to define product specifications and roadmaps. Provide technical leadership in tape-out planning, foundry interactions, and process node selection. Requirements: 7+ years of experience in RF/analog IC design, with a track record of silicon success. Strong understanding of RF system design principles, including impedance matching, noise figure optimization, and linearity. Expertise in Cadence Virtuoso, Spectre RF, ADS, HFSS, and EMX. Deep knowledge of CMOS/BiCMOS technologies and layout-aware design methodologies. Experience in full-chip integration and packaging considerations for RF ICs. Hands-on experience with RF lab characterization and debugging. Strong leadership, mentorship, and project management skills. Excellent communication and ability to work in a fast-paced startup environment.

Lead and manage the analog and RF layout team for high-performance semiconductor products Oversee layout planning, floorplanning, and routing for RF, analog, and mixed-signal IC designs. Work closely with circuit design teams to optimize layouts for performance, area, and manufacturability. Ensure DFM (Design for Manufacturability), DRC (Design Rule Check), LVS (Layout vs. Schematic), and EM (Electromigration) compliance. Drive automation and layout methodologies to improve efficiency and quality. Collaborate with foundry partners for process design kits (PDKs), layout guidelines, and tape-out requirements. Provide technical mentorship to layout engineers and review critical blocks. Own full-chip layout integration and support post-layout simulations. Qualifications: 8+ years of experience in analog/mixed-signal/RF IC layout. Strong expertise in FinFET (e.g., 16nm, 7nm, 5nm) or advanced CMOS nodes. Hands-on experience with Cadence Virtuoso, Calibre DRC/LVS, and Mentor Graphics tools. Knowledge of high-frequency layout techniques, parasitic-aware layout design, and shielding strategies. Experience in power management, high-speed SerDes, RF front-ends, or ADC/DAC layouts is a plus. Proven ability to lead teams, review layouts, and drive tape-out schedules. Strong understanding of wafer-level packaging and chip integration. Excellent problem-solving and communication skills.

At ABB, we help industries outrun - leaner and cleaner. Here, progress is an expectation - for you, your team, and the world. As a global market leader, we’ll give you what you need to make it happen. It won’t always be easy, growing takes grit. But at ABB, you’ll never run alone. Run what runs the world. This Position reports to: LPG Manager LVS IN Your Role And Responsibilities In this role, you will have the opportunity to adapt and implement sales support strategy for a designated area in accordance with the global support strategy. Each day, you will ensure technical and commercial support for internal and external customers. You will also showcase your expertise by overseeing estimations, bids, and proposals ensuring alignment with ABB standards and targets and leading, developing, and coaching the Sales Support team. In this role, you’ll help run what runs the world, by taking on meaningful work that drives real impact. The work model for the role is: This role is contributing to the Electrification business in Smart Power division at Nashik, India. You will be mainly accountable for: Defining key targets and ensuring their achievement by overseeing progress and defining improvement actions for customer support and satisfaction. Ensuring the most competitive offers considering the market situation and customer conditions; and identifying the most effective approach (e.g., direct sales, consortium, or channel) for better serving the customer. Overseeing the validation of terms and conditions (commercial, technical, legal, and pricing) in each offer; and supporting bid/no bid analyses and decisions. Participating in project risk review processes; and ensuring the required technical support and clarifications are provided to the Sales organizations during technical meetings, product presentations, and negotiations with customers. Our Team Dynamics Our teams support each other, collaborate, and never stop learning. Everyone brings something unique, and together we push ideas forward to solve real problems. Being part of our team means your work matters - because the progress we make here creates real impact out there. Qualifications For The Role You enjoy working with sales support function and the LV Switchgear market You have 8 to 12 years of experience in Estimation / Tendering of LV Switchgear / Panels You have hands on experience in managing the enquiries to meet the yearly budget with respect to order intake and margin, coordinating with engineering and project management and sales team Possess an enhanced knowledge of LV Switchgears (MCCB, ACB, PCC and MCC) Degree in Electrical engineering (should be full-time) You are at ease communicating in English More About Us (Mandatory) ABB Smart Power provides energy distribution solutions for data centers, industrial and manufacturing plants, critical infrastructure and commercial buildings. The Division’s technical teams work closely with industry partners, delivering advanced solutions that support rapid growth, energy transition, and sustainability objectives. The Division’s portfolio includes industrial circuit breakers, low-voltage systems, motor starting applications, and safety devices like switches and relays. Its Power Protection unit supports the world’s largest data center companies with advanced energy-efficient UPS solutions. The Division’s ABB Ability™ Energy Manager provides a scalable, easy-to-use platform that helps organizations save energy and reduce CO2 emissions. We value people from different backgrounds. Could this be your story? Apply today or visit www.abb.com to read more about us and learn about the impact of our solutions across the globe. Fraud Warning: Any genuine offer from ABB will always be preceded by a formal application and interview process. We never ask for money from job applicants. For current open positions you can visit our career website https://global.abb/group/en/careers and apply. Please refer to detailed recruitment fraud caution notice using the link https://global.abb/group/en/careers/how-to-apply/fraud-warning.

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies Familiarity with verification methodologies (UVM, System Verilog), testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Familiarity with high-level synthesis (HLS) tools Knowledge of scripting languages such as Python, Tcl, or Perl for automation Develop RTL designs using VHDL/Verilog for ASIC projects Perform digital logic design, synthesis, and timing analysis Conduct linting and static analysis to ensure code quality Develop and implement verification methodologies (UVM, System Verilog) Create and maintain testbenches for simulation and functional coverage Perform simulations and debugging to ensure design correctness Participate in design reviews and provide feedback to improve design quality

Hi Everyone!! Job Description: We are seeking an exceptional Physical Verification Engineer to take a key role in our semiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you will Responsible for development and implementation of cutting-edge physical verification methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodes for various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verification and sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Education: Bachelors Degree/Masters in ECE Location: Vishakapatnam

BENGALURU, KARNATAKA, INDIA FULL-TIME HARDWARE ENGINEERING 3559 Waymo is an autonomous driving technology company with the mission to be the most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo One, a fully autonomous ride-hailing service, and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over one million rider-only trips, enabled by its experience autonomously driving tens of millions of miles on public roads and tens of billions in simulation across 13+ U.S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms. In this hybrid role, you will report to an ASIC Design Manager This position will require the ability to work some hours that align with the team in the Pacific Daylight Time (PDT) zone on an as needed basis. You will: Participate in the Physical Design of advanced silicon for our self-driving cars Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS with a focus on floorplanning and assembly Collaborate with internal logic and internal and external PD teams to achieve the best PPA possible You have: 5+ years of experience on PD design tasks in advanced silicon nodes with a minimum of 2 tapeouts Expertise in generating and maintaining design-rule-check (DRC) clean floorplans (DEF) including pin placement and layer assignment and an understanding of abutted and non-abutted construction methodologies Familiarity with entire RTL-to-GDS flow with hands-on experience with Synthesis, PNR, STA, and timing closure Ability to automate EDA tasks through scripting. Competency with at least one EDA scripting language (TCL, skill, python) Excellent verbal and written communication skills due to need to work with internal and external teams We prefer: Experience with SDC generation, verification, and maintenance Experience working with external partners on PD closure Passion and experience for scripting (beyond driving EDA tools) Understanding of RC fundamentals Deep understanding of performance, power and area (PPA) tradeoffs Familiarity with back end flows (PI/SI, DRC/LVS, etc) May require infrequent travel to Mountain View, CA or to partner sites (Up to 15%) The expected base salary range for this full-time position is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range ₹5,500,000—₹6,650,000 INR

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. 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Exciting Opportunity for Physical Verification Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies. Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended. Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process. Address lithography and process variation concerns. Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication. Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process. Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress. Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations. Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues. Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics. Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process. Documentation: Maintain detailed documentation of verification processes, methodologies, and results. Qualifications:- BTECH/MTECH Experience:- The Engineers with 3 to 5+ years of Experience Location:- Bangalore/ Noida

Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Experience in Static Timing Analysis (STA) for ASIC designs Experience in developing timing constraints Experience in timing closure and optimization Proficiency in using scripting languages such as Perl and TCL Familiarity with EDA tools such as PrimeTime and Design Compiler Experience in Physical Design and/or DFT is a plus Bachelor s or Master s degree in Electrical/Electronics/Computer Science Engineering or related field

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. We are looking for Field Application Engineer for our custom IC Verification suite of products which are deployed across more than 400+ customers worldwide and growing exponentially. In this role, you will be an Applications Engineer who will play a critical role in our Customer Success Organization enabling the success of our customers in designing advanced chips on leading-edge process technologies. You will provide technical and engineering insight and direction to improving usability, applicability, and adoption of Solido Products involving statistical analysis, Monte Carlo, cell optimization and design sensitivity for Custom analog or foundation IPs. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest designs that customers are working on, and have the ability to influence at all levels, both internally and externally. Description Use in-depth product knowledge to provide technical expertise and support for our top customers. Diagnose, troubleshoot, and resolve complex technical issues on customer designs. Work directly with Research and Development (R&D) to develop and implement our technical roadmap, specifications, and validation for improvements and enhancements Partner with customers and Sales to identify business challenges, develop effective technical solutions, and increase utilization and retention of products on current accounts Drive business for Siemens, using technical expertise and working directly with customers at the appropriate management level to establish criteria for successful engagements Behavioural Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore whats possible to get the job done, including creative use of unconventional solutions Key Qualifications/Experience BE/ME EE, CS, CE or related discipline and 5-6+ years of experience Experience in circuit design and debugging skills is a big plus Good understanding of Statistical fundamentals and Monte Carlo Experience of working with Virtuoso/ADE is must Understanding of yield importance for standard cell/IO/memory and custom analog designs Experience with industry standard tools like Solido Variation aware, High Sigma monte carlo, Spectre fmc is added advantage Working knowledge of any of Spice simulators like AFS, Eldo, Finesim, Prime Sim, Hspice and Spectre is mandatory Working knowledge of scripting languages like Unix Shell, python is plus #DISW #LI-EDA #LI-Hybrid A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrows reality. Find out more about the Digital world of Siemens here/digitalminds Siemens Software. Where today meets tomorrow

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-7 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL