1017 Lvs Jobs - Page 4

The Opportunity The auxiliary design engineer has a responsibility to understand technical requirements for auxiliary power system networks and is fed with adequate power for the equipment and station to run without any interruption, there by ensuring safety of the end equipment and HVDC station as a whole. How You'll Make An Impact You will demonstrate knowledge in the design of MVS, LVS, Diesel Generator, Auxiliary/distribution Transformer & battery system. You will be responsible for the preparation of SLD, List of loads/load list/feeder list. You will be responsible for estimating material, equipment sizing activity (Diesel Generator & Auxiliary/Distribution transformer) and cable sizing...

Physical Design Lead Location: Bangalore We are a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. We are a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics. Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Di...

Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Excellent problem-solving skills in physical verification of custom layout. Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items....

We are looking for a skilled professional with 5-15 years of experience to join our team as an SCOM in IDESLABS PRIVATE LIMITED, located in [location to be specified]. The ideal candidate will have a strong background in recruitment services and excellent communication skills. Roles and Responsibility Manage and coordinate recruitment activities to meet client requirements. Develop and implement effective recruitment strategies to attract top talent. Build and maintain relationships with clients and candidates for successful placements. Conduct interviews and assessments to identify the best candidates. Collaborate with internal teams to ensure seamless recruitment processes. Analyze recruit...

Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/ Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete ownership on PNR implementatio n (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 20+ years Hardware Engineering experience or related work experience. 17+ years experience with PNR flo...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good unders...

Job Description: Broadcom is looking for a staff level physical design engineer. In this highly visible role, you will be contributing to ASIC for Storage/ AI products. Qualifications: Education and Experience : Master's degree in Electronics/Computer Engineering with over 10 years of experience in physical design. Physical Design Expertise : Extensive experience in Place & Route using Synopsys FC or Cadence Innovus tools is essential. Proficiency in STA using Primetime and/or Tempus. Demonstrated knowledge of Clock Tree Implementation Techniques for High-Speed Design Implementation. Ability to drive front-end and back-end implementation from RTL to GDSII, including synthesis, formal verific...

About SoftAge We partner with leading AI research labs and product teams to build and train large-scale models and agents. Our data has helped train frontier AI systems through advances in model training, reinforcement learning, computational physics, and large-scale data operations. Role Description We’re looking for experienced electrical engineers (3+ years of experience) with a background in circuit design and simulation. You may be a fit if you have Degree in Electrical Engineering or a related discipline 3-5+ years of professional experience in integrated circuit design, implementation, or verification. Hands-on experience with industry-standard EDA/CAD tools (e.g., Cadence, Synopsys, ...

Diploma / B.E / B.Tech from ECE/EEE 5+ years of experience. Experience in Schematic captures Component Creation, DRC Check, Design verification and BOM Creation. Experience in CADENCE Allegro PCB design and layout tools. Experience in High Speed board designs. Experience in High-speed Routing techniques (Good exposure in DDR routing, RF routings & Impedance control boards). Knowledge on EMI/EMC requirements. Knowledge on DFM and DFT for PCB. Knowledge on SI and THERMAL requirements. Hands on experience with Hypelynx tools for SI & thermal analysis is an added advantage. Experience in DRC Validation and Design Comparison. Experience in PCB Design Verification.

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Should have indepth experience in Floor-planning, CTS, Power routing, place and route, timing closure, DRC and LVS Should have worked on latest technology nodes (14nm or lesser) Should have worked on block level and top-level designs Good to have worked on designs without a customer flow. Strong problem-solving skills and communication skills. Ability to mentor and work closely with junior engineers Will be responsible for building a highly capable team of PD engineers at Ignitarium.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Will Include, But Are Not Limited To Develop and maintain quality systems and metrics to monitor and improve scribe design and assembly processes. Lead root cause analysis using tools like G8D, 5-Why, KT, and DITS to resolve quality issues. Build and maintain Technical Risk Assessment (TRA) documentation and communicate with assembly teams. Drive Business Process (BP) documenta...

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globa...

As a layout technical expert in analog-on-top ASIC developments, your role involves taking chip top ownership and being a hands-on technical contributor. You will collaborate within a global layout team and with cross-discipline stakeholders. Your responsibilities include: - Owning chip top layout and tape-out procedures - Independently going through required tape-out procedures and taking corrective actions - Taking ownership of internal layout flows, working on improvements and automation - Understanding foundry-specific constraints and optimizing internal tape-out checklists Qualifications required for this role include: - 15+ years of experience in custom analog layout - Experience with ...

As an experienced Layout Memory Engineer, your role will involve hands-on experience with important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. You should have a strong background in working with 16nm/14nm/10nm/7nm/Finfet process technologies and top-level memory integration, along with expertise in DRC, LVS, Density verification, and cleaning physicals across the compiler space. Your responsibilities will also include addressing IR/EM related issues in memory layouts and utilizing Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A solid understanding of ultra-de...

Job Description: Physical Design Should have in depth experience in Floor-planning, CTS, Power routing, place and route, timing closure, DRC and LVS Should have worked on the latest technology nodes (14nm or lesser). Must have experience in Static timing analysis Must have experience in Physical verification and appropriate fixes Should have worked on block level and top-level designs Good to have worked on designs without a customer flow. Strong problem-solving skills and communication skills. Ability to mentor and work closely with junior engineers Relevant Experience Required :- 7+Years Available Locations :- Bangalore, Kochi and Chennai

Overview: Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Physical engineer to join our Physical Design team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities: Complete ownership of Physical Design activities from Floorplan to GDS including PnR,STA,Physical Verification, Take compl...

Title : Power & Analog Layout Engineer About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com Introduction : As a Layout Engineer at GlobalFoundries Kolkata, you will work on gallium nitride and other power semiconductor technologies, contributing to custom p-cell development and layout...

Job Title : Physical Verification Engineer Location : Chennai, India Experience : 4- 6 Years Notice Period : Immediate to 15 Days Job Overview We are seeking a skilled Physical Verification Engineer to join our dynamic VLSI design team in Chennai. The ideal candidate will have hands-on experience in performing physical verification of complex SoC and ASIC designs, ensuring design compliance with foundry requirements and achieving sign-off quality results. Key Responsibilities Execute physical verification tasks including DRC, LVS, ERC, and Antenna checks using industry-standard tools. Collaborate with layout, P&R, and design teams to debug and resolve verification issues efficiently. Perform...

Responsibilities : Must have solid understanding of analog & mixed signal design fundamentals Design of basic analog IPs like LDOs, DC-DC converters, ADC/DACs, PLLs,Oscillators, Temperature sensors, Bandgap references and voltage monitors. Circuit design implementation of SERDES blocks like Transmitter, CTLE, SAL,DLL, Phase Interpolator, DFE and FFE Working Experience in Die to Die interconnect high speed IO designs, HBM, DDRand UCIe protocols. Hands on experience on lower FINFET technology nodes Basic analog layout knowledge especially with FINFET technology Expertise in following tools and standards: Cadence and Synopsys mixed signal design tool flow Requirements : The Candidate should hav...

Responsibilities: Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review cr...

Title : Power & Analog Layout Engineer About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com Introduction As a Layout Engineer at GlobalFoundries Kolkata, you will work on gallium nitride and other power semiconductor technologies, contributing to custom p-cell development and layout o...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The responsibility includes:-. -Independent planning and execution of Netlist-to-GDSII. -Good understanding of basics of static timing analysis. -Well versed with the Block level and SOC level timing closure (STA) methodologies, ECO generation and predictable convergence. -Should be able work in close collaboration with design, DFT and PNR team and resolve issues wrt constraints validation, verification, STA, Physical design, etc. -Should have good exposure to high frequency multi voltage design convergence. -Good understanding of clock networks. -Circuit level comprehension of timing critical paths in the...