423 Lvs Jobs - Page 4

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 2-5 years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux- Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 3+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelors or Masters degree from a top-tier institute. 6-8 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in complete Netlist2GDSFloorplan, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Hand on experience in lower technology nodes. Job Requirements: Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA. Managing and driving a small team for project execution and PPA targets Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a STA and Synthesis Engineer who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Synthesis, Static Timing Analysis and LEC of SoC/Cores Full chip and block level timing closure, IO budgeting for blocks Logical equivalence check between RTL to Netlist and Netlist to Netlist Knowledge of low-power techniques including clock gating, power gating and MV designs ECO timing flow Proficient in scripting languages (TCL and Perl). Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Responsibilities: 5 to 10 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Additional 7-14 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Additional Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing ]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 12+ years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum of 7+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Description Work with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification Coordinates with internal IP owners on IP related issues. Coordinates with Manufacturing Team on DRC related issues. Provide automation solutions to improve efficiency in tape-out flow. Report on tapeout issues. Custom Layout Requirement Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science 5-10 years of physical verification or design experience Preferably well-versed in Calibre, ICV Proficient in script programming, such as, Tcl, Perl or C-shell Proficient in UNIX (Linux) platforms Track record of successful tapeout of chips Strong communication skills, problem solving and analytical skills

Senior Standard Cell Layout Engineer Standard Cell Layout Designer Digital Layout Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and highly motivated professional with a robust technical background in standard cells layout design. Your passion for excellence and precision drives you to create layouts that set the standard for quality and manufacturability. You thrive in collaborative, cross-functional environments, seamlessly working with circuit designers, verification engineers, and other stakeholders to deliver optimized layout solutions. Your expertise in industry-leading EDA tools—such as Cadence Virtuoso or Synopsys Custom Compiler—enables you to tackle complex digital circuit layouts with efficiency and accuracy. Your systematic approach and strong problem-solving skills allow you to navigate technical challenges with ease, always seeking innovative ways to enhance design methodologies and best practices. You are deeply familiar with physical verification processes and design rule checks, ensuring that every layout you deliver meets stringent quality and manufacturability standards. Your curiosity and commitment to lifelong learning keep you updated on the latest advancements in standard cell layout design, making you an invaluable resource for your team. You communicate effectively, embrace feedback, and are eager to contribute to a culture of continuous improvement and shared success. What You’ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for digital circuits, ensuring alignment with project goals and timelines. Create and optimize complex standard cell layouts using industry-standard EDA tools such as Cadence Virtuoso or Synopsys Custom Compiler. Perform thorough physical verification and design rule checks (DRC/LVS) to guarantee design integrity and manufacturability. Work closely with circuit designers to understand design specifications, constraints, and performance targets, translating them into robust layouts. Contribute to the development, documentation, and refinement of layout design methodologies, flows, and best practices within the team. Remain up to date with industry trends, emerging technologies, and advancements in standard cell layout design, sharing knowledge with peers. The Impact You Will Have: Deliver high-quality layout designs that form the foundation of Logic Libraries IP development, essential for advanced SOC subsystems. Drive innovation in layout design methodologies, contributing to Synopsys’ leadership in the industry. Ensure that all designs meet or exceed manufacturability and reliability standards, reducing risk and time-to-market for key products. Collaborate effectively with circuit designers and verification teams to meet challenging design specifications and project milestones. Contribute to the overall success and reputation of the Logic Libraries IP group through your technical excellence and teamwork. Mentor and support junior team members, fostering a culture of knowledge-sharing and continuous improvement. What You’ll Need: Bachelor’s or master’s degree in electronics engineering or a related field. Minimum2 years of hands-on experience in standard cells layout design for digital circuits. Proficiency with industry-standard EDA tools, including Cadence Virtuoso or Synopsys Custom Compiler. Deep knowledge of layout design methods, techniques, and methodologies for high-performance and robust standard cells. Experience with physical verification tools such as ICC2, including DRC and LVS checks. Strong analytical and systematic problem-solving skills, with a detail-oriented mindset. Ability to work effectively in a collaborative, team-driven environment. Excellent communication and interpersonal skills, with a willingness to learn and share knowledge. Who You Are: A collaborative team player who values open communication and shared goals. Detail-oriented, with a commitment to delivering high-quality and reliable work. Curious and proactive, embracing continuous learning and professional development. Adaptable and resilient in the face of technical challenges and evolving requirements. Passionate about innovation, with a drive to improve processes and methodologies. Self-motivated, organized, and able to manage multiple priorities in a fast-paced environment. The Team You’ll Be A Part Of: You’ll join a dynamic and supportive Logic Libraries IP group focused on developing state-of-the-art standard cell libraries for advanced SOC subsystems. Our team thrives on collaboration, innovation, and technical excellence. We value diverse perspectives and foster an inclusive environment where every member’s contributions are recognized and celebrated. Together, we drive the success of Synopsys’ IP solutions, setting industry benchmarks and enabling our customers to achieve next-generation performance. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Senior Standard Cell Layout Engineer Standard Cell Layout Designer Digital Layout Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and highly motivated professional with a robust technical background in standard cells layout design. Your passion for excellence and precision drives you to create layouts that set the standard for quality and manufacturability. You thrive in collaborative, cross-functional environments, seamlessly working with circuit designers, verification engineers, and other stakeholders to deliver optimized layout solutions. Your expertise in industry-leading EDA tools—such as Cadence Virtuoso or Synopsys Custom Compiler—enables you to tackle complex digital circuit layouts with efficiency and accuracy. Your systematic approach and strong problem-solving skills allow you to navigate technical challenges with ease, always seeking innovative ways to enhance design methodologies and best practices. You are deeply familiar with physical verification processes and design rule checks, ensuring that every layout you deliver meets stringent quality and manufacturability standards. Your curiosity and commitment to lifelong learning keep you updated on the latest advancements in standard cell layout design, making you an invaluable resource for your team. You communicate effectively, embrace feedback, and are eager to contribute to a culture of continuous improvement and shared success. What You’ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for digital circuits, ensuring alignment with project goals and timelines. Create and optimize complex standard cell layouts using industry-standard EDA tools such as Cadence Virtuoso or Synopsys Custom Compiler. Perform thorough physical verification and design rule checks (DRC/LVS) to guarantee design integrity and manufacturability. Work closely with circuit designers to understand design specifications, constraints, and performance targets, translating them into robust layouts. Contribute to the development, documentation, and refinement of layout design methodologies, flows, and best practices within the team. Remain up to date with industry trends, emerging technologies, and advancements in standard cell layout design, sharing knowledge with peers. The Impact You Will Have: Deliver high-quality layout designs that form the foundation of Logic Libraries IP development, essential for advanced SOC subsystems. Drive innovation in layout design methodologies, contributing to Synopsys’ leadership in the industry. Ensure that all designs meet or exceed manufacturability and reliability standards, reducing risk and time-to-market for key products. Collaborate effectively with circuit designers and verification teams to meet challenging design specifications and project milestones. Contribute to the overall success and reputation of the Logic Libraries IP group through your technical excellence and teamwork. Mentor and support junior team members, fostering a culture of knowledge-sharing and continuous improvement. What You’ll Need: Bachelor’s or master’s degree in electronics engineering or a related field. Minimum2 years of hands-on experience in standard cells layout design for digital circuits. Proficiency with industry-standard EDA tools, including Cadence Virtuoso or Synopsys Custom Compiler. Deep knowledge of layout design methods, techniques, and methodologies for high-performance and robust standard cells. Experience with physical verification tools such as ICC2, including DRC and LVS checks. Strong analytical and systematic problem-solving skills, with a detail-oriented mindset. Ability to work effectively in a collaborative, team-driven environment. Excellent communication and interpersonal skills, with a willingness to learn and share knowledge. Who You Are: A collaborative team player who values open communication and shared goals. Detail-oriented, with a commitment to delivering high-quality and reliable work. Curious and proactive, embracing continuous learning and professional development. Adaptable and resilient in the face of technical challenges and evolving requirements. Passionate about innovation, with a drive to improve processes and methodologies. Self-motivated, organized, and able to manage multiple priorities in a fast-paced environment. The Team You’ll Be A Part Of: You’ll join a dynamic and supportive Logic Libraries IP group focused on developing state-of-the-art standard cell libraries for advanced SOC subsystems. Our team thrives on collaboration, innovation, and technical excellence. We value diverse perspectives and foster an inclusive environment where every member’s contributions are recognized and celebrated. Together, we drive the success of Synopsys’ IP solutions, setting industry benchmarks and enabling our customers to achieve next-generation performance. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Description The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS, etc. Requirements 3-8years of experience in ASIC Physical Design Have good knowledge of the entire physical design process from floorplan to GDSII generation Good Exposure to Physical Verification Process Have hands-on experience in the latest sub-micron technologies below 10 nm Hands–on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision

At ABB, we help industries outrun - leaner and cleaner. Here, progress is an expectation - for you, your team, and the world. As a global market leader, we’ll give you what you need to make it happen. It won’t always be easy, growing takes grit. But at ABB, you’ll never run alone. Run what runs the world. This Position reports to: LPG Manager LVS IN Your Role And Responsibilities In this role, you will have the opportunity to support the assigned Sales organization (division and market) and customers during the proposal process. Each day, you will serve as a key technical resource in the assigned area. You will also showcase your expertise by preparing technical descriptions of the products and technology, determining costs, and preparing final documentation. In this role, you’ll help run what runs the world, by taking on meaningful work that drives real impact. The work model for the role is: This role is contributing to the Electrification business in Smart Power division at Nashik, India. You will be mainly accountable for Offering technical advice and solutions on inquiries from customers/channels/Sales Specialists about ABB products/systems/applications. Performing analytic and diagnostic studies to determine the optimal technical solution to meet customer needs and address complex inquiries. Developing and maintaining new sales opportunities and resolving specific customer problems; and ensuring achievement of targets on orders, Net Price Variance (NPV), and Net Promoter Score (NPS). Ensuring the achievement of budget goals, including volume targets and profitable growth, across all assigned product groups and in the respective countries. Our Team Dynamics Our teams support each other, collaborate, and never stop learning. Everyone brings something unique, and together we push ideas forward to solve real problems. Being part of our team means your work matters - because the progress we make here creates real impact out there. Qualifications For The Role You enjoy working with sales support function and the LV Switchgear market You have 8 to 12 years of experience in Estimation / Tendering of LV Switchgear / Panels You have hands on experience in managing the enquiries to meet the yearly budget with respect to order intake and margin, coordinating with engineering and project management and sales team Possess an enhanced knowledge of LV Switchgears (MCCB, ACB, PCC and MCC) Degree in Electrical engineering (should be full-time) You are at ease communicating in English More About Us ABB Smart Power provides energy distribution solutions for data centers, industrial and manufacturing plants, critical infrastructure and commercial buildings. The Division’s technical teams work closely with industry partners, delivering advanced solutions that support rapid growth, energy transition, and sustainability objectives. The Division’s portfolio includes industrial circuit breakers, low-voltage systems, motor starting applications, and safety devices like switches and relays. Its Power Protection unit supports the world’s largest data center companies with advanced energy-efficient UPS solutions. The Division’s ABB Ability™ Energy Manager provides a scalable, easy-to-use platform that helps organizations save energy and reduce CO2 emissions. We value people from different backgrounds. Could this be your story? Apply today or visit www.abb.com to read more about us and learn about the impact of our solutions across the globe. Fraud Warning: Any genuine offer from ABB will always be preceded by a formal application and interview process. We never ask for money from job applicants. For current open positions you can visit our career website https://global.abb/group/en/careers and apply. Please refer to detailed recruitment fraud caution notice using the link https://global.abb/group/en/careers/how-to-apply/fraud-warning.

Job description Company: ARF Design Pvt Ltd Location: Bhubaneswar and Ranchi Employment Type: Full-Time | Permanent Working Days: Monday to Saturday Interview Mode: Face-to-Face Job Description:– Analog Layout Engineer We are actively hiring Analog Layout Engineers with 3+ years of industry experience. Ideal candidates must have solid expertise in lower technology nodes, physical layout techniques, and verification processes. ARF provides an excellent platform to work on advanced nodes with fast-track interview and onboarding processes. Key Responsibilities: ● Design and development of analog layout IP blocks and full-chip integration ● Perform and resolve LVS/DRC violations independently ● Collaborate with circuit design teams to optimize layout quality and performance ● Ensure layouts meet design matching and parasitic constraints ● Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: ● 3+ yrs of relevant Analog Layout experience ● Proficiency in LVS/DRC checks and EDA tools ● Experience with lower technology nodes (3nm,5nm,7nm,10, 16nm / 28nm ETC) ● Good understanding of layout matching, parasitic extraction, and floor planning ● Strong verbal and written communication skills ● Ability to work independently and within cross-functional teams Job Description:– Circuit Design Engineer ARF Design is hiring Analog Mixed Signal Designers to work on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. Key Responsibilities: ● Derive circuit block level specifications from top level specifications ● Perform optimized transistor-level design of analog and custom digital blocks ● Run SPICE simulations to meet detailed specifications ● Guide layout design for best performance, matching, and power delivery ● Characterize design performance across PVT + mismatch corners and reliability checks (aging, EM, IR) ● Generate and deliver behavioral (Verilog), timing (LIB), and physical (LEF) models of circuits ● Conduct design reviews at various phases/maturity of the design Qualifications: ● BE/M-Tech in Electrical & Electronics ● Strong fundamentals in RLC circuits, CMOS devices and digital design concepts (e.g., counters, FSMs) ● Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators ● Collaborative mindset with a positive attitude Exp: 3+ Please share updated resume [Name_Post_Exp] to divyas@arf-desgn.com Job Types: Full-time, Permanent Work Location: In person

Job Description We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. How You Will Contribute And What You Will Learn Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices. Key Skills And Experience You have: Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies About Us Come create the technology that helps the world act together Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people’s lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world. We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work What we offer Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered. Nokia is committed to inclusion and is an equal opportunity employer Nokia has received the following recognitions for its commitment to inclusion & equality: One of the World’s Most Ethical Companies by Ethisphere Gender-Equality Index by Bloomberg Workplace Pride Global Benchmark At Nokia, we act inclusively and respect the uniqueness of people. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect. Join us and be part of a company where you will feel included and empowered to succeed. About The Team Nokia Bell Labs is the world-renowned research arm of Nokia, having invented many of the foundational technologies that underpin information and communications networks and all digital devices and systems. This research has produced nine Nobel Prizes, five Turing Awards and numerous other awards.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role Join AMD as we push the boundaries of what's possible in graphics and compute technology. We are seeking a talented RTL Physical Design Engineer to contribute to the development and optimization of our cutting-edge CDNA and RDNA graphics IP. This role involves transforming sophisticated RTL designs into robust and efficient physical layouts, critical to the performance of our next-generation graphics and compute solutions. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Physical Design Implementation: Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts. Utilize industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes to take the design thru mock-taepout Performance Optimization: Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products. Collaborate with architecture and front-end design teams to align RTL design with physical constraints and objectives. Verification and Timing Closure: Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP. Implement and verify design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements. Collaboration and Communication: Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores. Provide feedback and suggest improvements to design methodologies and processes to push the technology envelope further. Documentation and Reporting: Maintain comprehensive design documentation, methodologies, and updates. Prepare detailed reports on design progress, performance metrics, and any technical challenges encountered. PREFERRED EXPERIENCE: Domain Expertise: Experience with working on complex design and optimizing for performance, power, and area. Technical Proficiency: Proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores. Proficiency with industry-leading EDA tools, such as Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like PrimeTime. Experience with low-power design methodologies and techniques for high-performance graphics IP. Design and Verification: Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks. Strong skills in signal integrity analysis, including crosstalk and IR drop evaluations. Process Technology: Experience working with advanced semiconductor process nodes (e.g., 7nm, 5nm, or below). Knowledge of process-related challenges and optimization techniques for graphics applications. Scripting and Automation: Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency. Experience developing and maintaining scripts for design rule checks and optimization processes. Problem-Solving and Innovation: Demonstrated ability to solve complex design challenges using innovative approaches. A track record of contributing to the improvement of design techniques and methodologies in a graphics-focused engineering team. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Exciting Opportunity for Physical Verification Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies. Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended. Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process. Address lithography and process variation concerns. Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication. Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process. Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress. Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations. Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues. Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics. Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process. Documentation: Maintain detailed documentation of verification processes, methodologies, and results. Qualifications:- BTECH/MTECH Experience:- The Engineers with 5+ years of Experience Location:- Bangalore/ Noida

Company: ARF Design Pvt Ltd Location: Bhubaneswar and Ranchi Employment Type: Full-Time | Permanent Working Days: Monday to Saturday Interview Mode: Face-to-Face Job Description:– Analog Layout Engineer We are actively hiring Analog Layout Engineers with 3+ years of industry experience. Ideal candidates must have solid expertise in lower technology nodes, physical layout techniques, and verification processes. ARF provides an excellent platform to work on advanced nodes with fast-track interview and onboarding processes. Key Responsibilities: ● Design and development of analog layout IP blocks and full-chip integration ● Perform and resolve LVS/DRC violations independently ● Collaborate with circuit design teams to optimize layout quality and performance ● Ensure layouts meet design matching and parasitic constraints ● Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: ● 3+ yrs of relevant Analog Layout experience ● Proficiency in LVS/DRC checks and EDA tools ● Experience with lower technology nodes (3nm,5nm,7nm,10, 16nm / 28nm ETC) ● Good understanding of layout matching, parasitic extraction, and floor planning ● Strong verbal and written communication skills ● Ability to work independently and within cross-functional teams Job Description:– Circuit Design Engineer ARF Design is hiring Analog Mixed Signal Designers to work on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. Key Responsibilities: ● Derive circuit block level specifications from top level specifications ● Perform optimized transistor-level design of analog and custom digital blocks ● Run SPICE simulations to meet detailed specifications ● Guide layout design for best performance, matching, and power delivery ● Characterize design performance across PVT + mismatch corners and reliability checks (aging, EM, IR) ● Generate and deliver behavioral (Verilog), timing (LIB), and physical (LEF) models of circuits ● Conduct design reviews at various phases/maturity of the design Qualifications: ● BE/M-Tech in Electrical & Electronics ● Strong fundamentals in RLC circuits, CMOS devices and digital design concepts (e.g., counters, FSMs) ● Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators ● Collaborative mindset with a positive attitude Exp: 3+ Please share updated resume [Name_Post_Exp] to divyas@arf-desgn.com

As a Layout Design Engineer at Micron Technology, you will play a crucial role in developing critical analog, mixed-signal, and custom digital blocks. Your responsibilities will include designing and developing layout designs, performing layout verification such as LVS/DRC/Antenna, conducting quality checks, and providing support documentation. It will be your responsibility to ensure timely delivery of block-level layouts with acceptable quality while taking ownership of area estimation, scheduling, and execution to meet project deadlines. Collaboration with team members and being a supportive team player are essential aspects of this role. To be successful in this position, you should have 2 to 5 years of experience in analog/custom layout design in advanced CMOS and FinFET processes across various technologies and foundries ranging from 16nm to 130nm. Proficiency in tools like Cadence Virtuoso GXL/XL and DRC/LVS/Extraction (Cadence/Mentor Graphics/Synopsys) is a must. Hands-on experience in creating layouts of critical blocks such as LDO, Bandgap, Ref Generators, and Oscillator is required. A strong understanding of Analog Layout fundamentals, including Matching, Electromigration, Latch-up, coupling, crosstalk, IR-drop, and active/passive parasitic devices, is essential. You should also possess the ability to comprehend design constraints and implement high-quality layouts. Problem-solving skills in physical verification (LVS/DRC/Antenna/PEX) of custom layouts and knowledge of scripting languages like Skill, Python, Perl, TCL, SVRF, etc., will be beneficial. A passion for continuous learning, innovation, success, and teamwork is highly valued in this role. Micron Technology, Inc., is a global leader in memory and storage solutions, dedicated to transforming how information enriches lives worldwide. With a focus on technology leadership, operational excellence, and customer satisfaction, Micron offers a wide range of high-performance DRAM, NAND, and NOR memory and storage products under the Micron and Crucial brands. The innovative solutions developed by Micron's talented workforce drive the data economy, enabling advancements in artificial intelligence and 5G applications across various platforms. If you are excited about contributing to cutting-edge technology and being part of a dynamic team at Micron Technology, please visit micron.com/careers for more information. For assistance with the application process or to request reasonable accommodations, please reach out to hrsupport_india@micron.com. Micron Technology strictly prohibits the use of child labor and adheres to all relevant laws, regulations, and international labor standards.,

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

About Tata Electronics: Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence. Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust. Key Responsibilities: Collaborate with customers to understand their design requirements and provide technical support throughout the phase. Identify, troubleshoot, and resolve design issues such as DRC, LVS, and other verification checks to ensure successful tapeout. Layout Design, Knowledge of layout techniques to optimize performance . Assist in the tapeout process, ensuring all design files are correctly prepared and submitted for manufacturing. Hands-on in relevant EDA tools like Virtuoso, Custom compiler, Calibre , PrimeTime etc Candidate willing to travel to customer sites ad hoc. Qualifications: Bachelor’s or master’s degree in electrical engineering or a related field. Proven experience of at least 8 years as analog chip designer/customer support. Strong problem-solving skills and ability to work under pressure. Excellent communication and interpersonal skills. Hands-on in EDA tools such as Cadence , Synopsys and Mentor Graphics Knowledge of Tapeout processes and GDS file preparation.

As a Layout Design Engineer at Micron Technology, you will be responsible for the design and development of critical analog, mixed-signal, and custom digital blocks. Your role will involve performing layout verification tasks such as LVS/DRC/Antenna checks, ensuring quality, and supporting documentation. It will be crucial for you to deliver block-level layouts on time with acceptable quality, taking ownership of area estimation, scheduling, and execution to meet project deadlines. Collaboration with team members and being a strong team player are essential aspects of this role. To qualify for this position, you should have 2 to 5 years of experience in analog/custom layout design in advanced CMOS and Finfet processes across various technologies and foundries ranging from 16nm to 130nm. Expertise in tools like Cadence Virtuoso GXL / XL and DRC / LVS / Extraction (Cadence / Mentor Graphics / Synopsys) is a must. Hands-on experience in creating layouts of critical blocks such as LDO, Bandgap, Ref Generators, Oscillator, etc., is required. A solid understanding of Analog Layout fundamentals and their impact on circuit performance is essential. You should be capable of implementing high-quality layouts while considering design constraints and solving physical verification challenges effectively. Moreover, familiarity with scripting languages such as Skill, Python, Perl, TCL, SVRF, etc., is beneficial for this role. A passion for continuous learning, innovation, success, and teamwork will drive your success as part of our dynamic team. Micron Technology, Inc. is a global leader in memory and storage solutions, committed to transforming how information enriches life for all. Our focus on customers, technology leadership, operational excellence, and product innovation sets us apart in the industry. Through our Micron and Crucial brands, we deliver a diverse portfolio of high-performance DRAM, NAND, and NOR memory and storage products that power the data economy, enabling advancements in artificial intelligence and 5G applications. To explore career opportunities with Micron Technology, please visit micron.com/careers. For any assistance with the application process or to request reasonable accommodations, please reach out to hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all relevant laws, rules, regulations, and international labor standards.,