1019 Lvs Jobs - Page 11

Analog Layout Design Engineer www.sevyamultimedia.com Hyderabad About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. Chip Design Services Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC Analog Layout Design Engineer with 3+ years of relevant work experience You will be doing Analog Layout in advanced process ...

Analog Layout Design Engineer www.sevyamultimedia.com Hyderabad About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. Chip Design Services Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC Analog Layout Design Engineer with 3+ years of relevant work experience You will be doing Analog Layout in advanced process ...

Company Description Tecquire Solutions Private Limited is a comprehensive provider of semiconductor design services. The company was founded by a team with over 25+ years of experience in the semiconductor industry. Tecquire Solutions provides tailored services in the areas of DFT architecture, DFT implementation, silicon debug, pattern reduction, and Netlist to GDSII implementation. The company has a strong track record of successful SOC design and first-time silicon success across multiple tape-outs. Job Summary: We are seeking an experienced and strategic Director of Physical Design to lead and grow our physical design team responsible for the implementation of complex SoC and ASIC design...

DV lead/manager www.sevyamultimedia.com Hyderabad About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. Chip Design Services Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC DV lead/manager to verify IP/SoC using System Verilog/UVM --------------------------------------------------------------------------------...

As a Physical Verification Engineer for SOC/blocks, your role involves performing physical verification for SOCs, cores, and blocks, which includes tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. You will be responsible for addressing critical design and execution challenges related to physical verification and sign-off. It is essential for you to have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Collaboration with PNR engineers to achieve sign-off at various stages of the design process is also a key aspect of your role. Your qualifications and skills should include proficiency in physical verification for SoC/full-chip and b...

We are looking for a skilled professional with 5-15 years of experience to join our team as an SCOM in IDESLABS PRIVATE LIMITED, located in [location to be specified]. The ideal candidate will have a strong background in recruitment services and excellent communication skills. Roles and Responsibility Manage and coordinate recruitment activities to meet client requirements. Develop and implement effective recruitment strategies to attract top talent. Build and maintain relationships with clients and candidates for successful placements. Conduct interviews and assessments to identify the best candidates. Collaborate with internal teams to ensure seamless recruitment processes. Analyze recruit...

We are looking for a skilled SAP DRC Engineer with 7 to 12 years of experience. The ideal candidate will have expertise in the SAP DRC module and BTP of SAP, SD, FI, E-Doc Cockpit, and project management skills. This position is available in PAN India, including Bangalore, Hyderabad, Chennai, Noida, Pune, and Gurgaon. Roles and Responsibility Design and implement SAP DRC solutions to meet business requirements. Collaborate with cross-functional teams to ensure seamless integration of SAP DRC with other modules. Develop and maintain documentation for SAP DRC projects. Provide training and support to end-users on SAP DRC functionality. Troubleshoot and resolve technical issues related to SAP D...

Analog Layout Design Engineer with 3+ years of relevant work experience You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients. What you get: Inducted in the advanced Analog VLSI projects Get an opportunity to work with clients that are world-class VLSI MNCs Skills: Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre) Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators Physical Verification ( LVS, DRC, ERC, ANT with Cal...

We are looking for a skilled Observability Engineer with 4 to 7 years of experience. The ideal candidate will have expertise in Data Integration & Standardization, OTEL, Java, Python, or frontend languages, and Grafana. This position is available in Bangalore, Mumbai, Chennai, Hyderabad, Noida, and Gurgaon. Roles and Responsibility Design and implement data integration solutions using various tools and technologies. Develop and manage data aggregation techniques to ensure data quality and integrity. Collaborate with cross-functional teams to identify and prioritize project requirements. Implement and manage data ingestion pipelines to support business intelligence initiatives. Troubleshoot a...

We are looking for a skilled professional with 7 to 15 years of experience in the field of Physical Design to join our team. The ideal candidate will have a strong background in Floor Planning, Innovus, Fusion Compiler, and programming skills in Tcl/Tk/Perl. Roles and Responsibility Develop and implement physical design methodologies for submicron technology nodes. Utilize expertise in Floor Planning, Innovus, and Fusion Compiler to optimize design performance. Collaborate with cross-functional teams to ensure seamless integration of physical design with other components. Apply knowledge of physical design principles and methodologies to improve design quality. Troubleshoot and debug complex...

Analog Layout Design Lead with 7+ years of relevant work experience You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients. What you get: Inducted in the advanced Analog VLSI projects Get an opportunity to work with clients that are world-class VLSI MNCs Skills: Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre) Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators Physical Verification ( LVS, DRC, ERC, ANT with Calibre...

Education Requirements B. Tech / M. Tech (ECE) Experience 3 to 13 Years Job Location Hyderabad Shift General (No WFH) Work Week Monday to Friday He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. · Provide technical guidance, mentoring to physical design engrs. · Interf...

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualificatio...

Skill : Analog Layout Location - Hyderabad Experience - 5+Years JD: Skill: TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience. 1. TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience. 2. Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. 3. Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience. 4. Responsible for on-time delivery of block-level layouts of acceptable quality. 5. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. 6...

Role Overview: As an Auxiliary Design Engineer, you will have the responsibility to understand technical requirements for auxiliary power system networks to ensure that equipment and stations run smoothly without interruptions, ultimately guaranteeing the safety of the end equipment and HVDC station as a whole. Key Responsibilities: - Demonstrate knowledge in the design of MVS, LVS, Diesel Generator, Auxiliary/distribution Transformer & battery system. - Prepare SLD, List of loads/load list/feeder list. - Estimate material, equipment sizing activity (Diesel Generator & Auxiliary/Distribution transformer) and cable sizing (LV & MV). - Revisit and update processes based on feedback. - Coordina...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

The Opportunity The auxiliary design engineer has a responsibility to understand technical requirements for auxiliary power system networks and is fed with adequate power for the equipment and station to run without any interruption, there by ensuring safety of the end equipment and HVDC station as a whole. How You'll Make An Impact You will demonstrate knowledge in the design of MVS, LVS, Diesel Generator, Auxiliary/distribution Transformer & battery system. You will be responsible for the preparation of SLD, List of loads/load list/feeder list. You will be responsible for estimating material, equipment sizing activity (Diesel Generator & Auxiliary/Distribution transformer) and cable sizing...

The Opportunity The auxiliary design engineer has a responsibility to understand technical requirements for auxiliary power system networks and is fed with adequate power for the equipment and station to run without any interruption, there by ensuring safety of the end equipment and HVDC station as a whole. How You'll Make An Impact You will demonstrate knowledge in the design of MVS, LVS, Diesel Generator, Auxiliary/distribution Transformer & battery system. You will be responsible for the preparation of SLD, list of loads/load list/feeder list. You will be responsible for estimating material, equipment sizing activity (Diesel Generator & Auxiliary/Distribution transformer) and cable sizing...

The Opportunity The auxiliary design engineer has a responsibility to understand technical requirements for auxiliary power system networks and is fed with adequate power for the equipment and station to run without any interruption, there by ensuring safety of the end equipment and HVDC station as a whole. How You'll Make An Impact You will demonstrate knowledge in the design of MVS, LVS, Diesel Generator, Auxiliary/distribution Transformer & battery system. You will be responsible for the preparation of SLD, List of loads/load list/feeder list. You will be responsible for estimating material, equipment sizing activity (Diesel Generator & Auxiliary/Distribution transformer) and cable sizing...

The Opportunity We are looking for a detail-oriented and innovative Lithography Mask Designer with strong programming skills to support our semiconductor development processes. In this role, you will be responsible for the creation, optimization, and automation of lithography mask layouts, ensuring precision and efficiency in advanced manufacturing environments. How You’ll Make An Impact You will design and generate lithography masks for semiconductor devices using industry-standard tools (e.g. Cadence, KLayout, Calibre), big plus would be knowledge of DW2000. You will collaborate with process engineers and product designers to translate device requirements into mask layouts. You will develo...

Roles and Responsibilities Design analog layouts using Cadence Virtuoso for FinFET devices with PLL and SerDes interfaces. Perform DRC, LVS, and mixed signal simulations to ensure design integrity. Collaborate with cross-functional teams to resolve design issues and optimize designs. Develop expertise in Caliber technology for high-speed I/O applications. Ensure compliance with industry standards and company guidelines.

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

Responsibilities Perform full-custom analog layout for advanced nodes (28nm and below ,TSMC,FinFET/CMOS technologies) .Work on block-level and top-level layouts of circuits such as: PLLs, ADCs, DACs, LDOs, Bandgaps, High-speed IOs, SerDes, RF blocks

Responsibilities: Must have solid understanding of analog & mixed signal design fundamentals Design of basic analog IPs like LDOs, DC-DC converters, ADC/DACs, PLLs,Oscillators, Temperature sensors, Bandgap references and voltage monitors. Circuit design implementation of SERDES blocks like Transmitter, CTLE, SAL,DLL, Phase Interpolator, DFE and FFE Working Experience in Die to Die interconnect high speed IO designs, HBM, DDRand UCIe protocols. Hands on experience on lower FINFET technology nodes Basic analog layout knowledge especially with FINFET technology Expertise in following tools and standards: Cadence and Synopsys mixed signal design tool flow Requirements: The Candidate should have ...