425 Lvs Jobs - Page 10

Job Summary Physical verification engineer for SOC/blocks Key Responsibilities • Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. • Address critical design and execution challenges associated with physical verification and sign-off. • Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. • Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications and Skills Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tapeout. • Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. • Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. • Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. • Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. • Capable of developing sign-off methodologies/flows and providing support to larger teams. • Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. • Experience in floorplanning is a plus. Show more Show less

BoltChip builds Global Capability Centres (GCCS) for semiconductor IC Design and AI innovation companies in ASIA Role : Senior Layout Engineer – TSMC 12nm and Below Location: Gujarat Experience: 5+ years Industry: Semiconductor Design About the Role: We are seeking an experienced Senior Layout Engineer to join our semiconductor design team. This role is ideal for professionals with a solid background in deep sub-micron technologies and hands-on experience in analog layout, particularly with TSMC 12nm and below process nodes. Key Responsibilities: Execute full custom layout for analog and mixed-signal blocks including IO (TX and RX), PLLs , and other analog circuits. Ensure high-quality layout design aligned with DRC, LVS, and EMIR compliance using industry-standard tools. Collaborate closely with circuit design teams and physical verification engineers to resolve layout issues. Participate in design reviews and contribute to layout planning and optimization. Maintain quality and performance standards in high-speed, low-power layout design. Required Qualifications: 5+ years of experience in custom analog/mixed-signal layout. Proven hands-on experience on TSMC 12nm or smaller technology nodes. Direct experience for at least 1–2 years in layout of IO blocks (TX/RX) , PLLs , and various analog IP blocks . Proficient with tools like Virtuoso, Calibre, and Assura. Strong understanding of parasitic extraction, signal integrity, and layout best practices. Ability to work independently and in collaboration with cross-functional teams. Preferred Qualifications: Experience with lower nodes such as 7nm or 5nm is a plus. Exposure to ESD, latch-up protection, and high-speed signaling considerations. Why Join Us? Be part of a fast-growing semiconductor design group working on cutting-edge technology. You’ll collaborate with some of the sharpest minds in the industry and help shape the future of SoC innovation. Show more Show less

Your Job The PCB Designer will be responsible for creating and optimizing PCB layouts, ensuring high-quality design for manufacturability, reliability, and performance. This position requires strong knowledge of PCB design principles, proficiency in design software, and a collaborative approach to work effectively with cross-functional teams, including hardware, firmware, signal integrity, and manufacturing. Our Team The PCB Design Engineering Team at Koch Industries is a talented and innovative group dedicated to developing state-of-the-art hardware solutions. We work collaboratively across disciplines to design, prototype, and test high-quality hardware components that support our company's growth and technological advancements. Join us to be part of a dynamic team that values creativity, excellence, and teamwork. What You Will Do PCB Layout Design: Design multi-layer PCB layouts for high-speed, high-density, and complex circuits, ensuring compliance with electrical, mechanical, and DFM (Design for Manufacturability) guidelines. Schematic Integration: Collaborate with electrical engineers to interpret and incorporate schematic designs into PCB layouts, ensuring accurate component placement and routing. Signal and Power Integrity: Work with SI/PI engineers to integrate design constraints and guidelines for high-speed signals, impedance control, and power distribution. Design Verification: Conduct Design Rule Checks (DRC), Layout vs. Schematic (LVS) checks, and other design verification processes to ensure design integrity and accuracy. Component Library Management: Create and maintain a library of PCB footprints and symbols, ensuring adherence to company standards and industry best practices. Documentation: Generate detailed fabrication and assembly documentation, including Gerber files, BOMs, and assembly drawings, ensuring clear instructions for manufacturing partners. Collaboration and Communication: Work closely with cross-functional teams, including hardware engineers, manufacturing, and quality control, to support design iterations, review processes, and resolve technical issues. Who You Are (Basic Qualifications) BE/B Tech in Electrical/Electronic & Communication Engineering 4 to 6 years of demonstrable experience as a PCB Design engineer. Education: Bachelor’s degree in Electronics Engineering, Electrical Engineering, or a related field (or equivalent experience). Experience: Minimum of 3-5 years of experience in PCB design, preferably with high-speed and/or complex multilayer boards. What Will Put You Ahead Technical Skills: Proficiency in PCB design software (Altium Designer, Cadence Allegro, or equivalent). Familiarity with IPC standards (CID certification is a plus). Strong understanding of high-speed design practices, including signal integrity, impedance control, and EMI/EMC considerations. Knowledge of design for manufacturability (DFM) and design for testability (DFT) principles. Soft Skills: Strong attention to detail and commitment to delivering high-quality designs. Effective communication skills to work with cross-functional teams and present design considerations. Problem-solving skills and adaptability to new tools and design challenges. At Koch companies, we are entrepreneurs. This means we openly challenge the status quo, find new ways to create value and get rewarded for our individual contributions. Any compensation range provided for a role is an estimate determined by available market data. The actual amount may be higher or lower than the range provided considering each candidate's knowledge, skills, abilities, and geographic location. If you have questions, please speak to your recruiter about the flexibility and detail of our compensation philosophy. Who We Are Molex is a subsidiary of Koch Industries, an MNC and industry leader in electronic solutions. We support a wide range of industries like data communications, consumer electronics, industrial, automotive, medical etc. Our presence is in 223 locations across 40 countries. We have a portfolio of 100,000 electronic products and a dedicated R&D facility driving technological innovation in Bangalore. We make a connected world possible to enable technology that transforms the future. Connected Mobility Solutions (CMS), a business unit of Molex, develops innovative products and manufacturing processes around automotive in-vehicle networking, infotainment, and lighting segments. You may not see our name on the shelves, but our electronic solutions are inside the products you use every day. We work together with the world’s innovators to design and manufacture electronic solutions that solve complex technical challenges. From innovative products like high-speed USB and LVDS signaling to mini coax 25Gb+ Ethernet solutions, media modules, Wireless chargers, we design, develop and manufacture products that enable flawless data transfer, electric charging within the next generation of autonomous and connected vehicles. At Molex, we not only employ some of the most talented people from all over the world, we work to help cultivate tomorrow's breakthroughs. From our corporate headquarters in Lisle, IL to manufacturing floors around the world, the Molex team is dedicated to helping further the limits of technology. For further information: https://www.molex.com/molex/home https://www.youtube.com/watch?v=gQW5D50-4kM https://www.youtube.com/watch?v=LAlRFVN7Ke8 https://www.youtube.com/watch?v=fQJarCeJz0A https://www.youtube.com/watch?v=nwzSp5TvLUM At Koch, employees are empowered to do what they do best to make life better. Learn how our business philosophy helps employees unleash their potential while creating value for themselves and the company. Additionally, everyone has individual work and personal needs. We seek to enable the best work environment that helps you and the business work together to produce superior results. We are currently building our in-house Engineering staff and are looking for a talented, proactive PCB Design engineer to join our team. If you are looking for a way to accelerate your career and be part of a great company, this may be the opportunity for you. In this role you will have the opportunity to Manage all PCB Design activities in a product program Show more Show less

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tape out. Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floor planning is a plus Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. I'm interested Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tape out. Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floor planning is a plus Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. I'm interested Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Lead Physical Design Engineer | Hyderabad, India | Experience : 8+ Years Domain : Semiconductor – Physical Design About the Role: We are looking for a Lead Physical Design Engineer with deep expertise in working on mature/legacy nodes such as 180nm, 130nm, 110nm, 90nm, 65nm, 45nm, 40nm . This role involves end-to-end ownership of physical design flow, from floorplanning to GDSII, with a strong emphasis on timing closure, IR/EM analysis, and physical verification . The ideal candidate should be technically hands-on and able to lead block-level or chip-level efforts with minimal supervision. Key Responsibilities: End-to-end execution of RTL to GDSII physical design for block- or full-chip Perform floorplanning, placement, clock tree synthesis (CTS), routing, and signoff Manage timing closure , IR drop, EM, and congestion challenges effectively Handle physical verification (LVS, DRC, ERC, antenna checks) using standard sign-off tools Work closely with RTL, STA, DFT, and package integration teams Mentor junior team members and support physical design reviews and planning Required Skills: Proven experience on older technology nodes (e.g., 180nm, 130nm, 110nm, 90nm, 65nm, 45nm, 40nm ) Hands-on with tools like Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre, StarRC Expertise in timing constraints, physical ECOs , and sign-off methodologies Strong understanding of low power design, DFM, and hierarchical flows Ability to lead technically and communicate effectively across teams Educational Qualification: B.E./B.Tech or M.E./M.Tech in Electronics, VLSI Design, or related disciplines Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com Show more Show less

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times Initiate & drive cost out measures Explore new suppliers & expedite development Maintain business relationship with all supplier for best outcome Travelling /Visit to suppliers required. (As per business requirement) Excellent Communication skills (Written/Oral)

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Responsibilities: Assist in the development and validation of PDKs for various process nodes. Support the integration of technology files, DRC/LVS decks, and device models into EDA tools (e.g., Cadence, Synopsys). Write and maintain automation scripts (e.g., Python, TCL, Shell) to streamline PDK development processes. Collaborate with layout, design, and modeling teams to ensure PDK accuracy and usability. Troubleshoot and fix issues in PDK components related to DRC, LVS, parasitic extraction, and schematic symbols. Document PDK features, known issues, and development changes. Show more Show less

Tenstorrent is at the forefront of cutting-edge AI technology, redefining what’s possible in performance, usability, and cost. As AI transforms the computing landscape, it demands integrated innovation across software models, compilers, platforms, networking, and semiconductors. Our team—diverse, curious, and driven—has built a high-performance RISC-V CPU from the ground up and shares a collective passion for advancing AI. We thrive on collaboration and tackling tough challenges, and we’re expanding our team across all experience levels. We’re looking for an experienced CPU/IP / SoC Physical Verification Engineer who can take ownership of full-chip and block-level physical verification across our complex RISC-V based designs. This role is ideal for someone who thrives in a fast-paced, collaborative environment, enjoys solving challenging problems across advanced technology nodes, and is passionate about building clean, manufacturable silicon. What You’ll Be Doing Drive physical verification activities (DRC, LVS, ERC, PERC, Antenna, DFM) from block to full-chip level. Collaborate closely with RTL, PD, CAD, and packaging teams to ensure sign-off readiness. Debug verification issues and work hands-on with tools like Calibre and ICV to root-cause violations. Support ESD planning, padring integration, and bump/RDL layout strategies. Contribute to PV methodology improvements and automation scripts. Lead PV closure for key tapeouts and provide mentorship to junior engineers on the team. Interface with foundry teams for rule deck alignment and tapeout planning. What We’re Looking For 6 to 14 years of hands-on experience in CPU/IP / SoC physical verification. Solid command of physical verification tools and flows (Calibre, ICV, ICC2, Innovus, etc.). Strong understanding of advanced node requirements (7nm, 5nm, 3nm), including FinFET challenges. Proficiency in checking and resolving DRC, LVS, ERC, and PERC violations. Comfortable scripting in Python, TCL, or Perl to automate workflows and debug processes. Awareness of ESD, IR drop, EM, and reliability considerations in full-chip designs. Clear communication and a strong sense of ownership — you enjoy working across teams and taking designs across the finish line. Show more Show less

We are looking for a skilled Standard Cell Layout Engineer with 3 – 5 Years of experience in standard cell, Analog, mixed-signal, and custom digital block layout design using advanced CMOS technologies . The candidate should have strong hands-on experience with Cadence Virtuoso for schematic and layout editing and be proficient in physical verification (DRC/LVS) using tools like Mentor Calibre Position: Standard Cell Layout Engineer Location: Phoenix Aquila, Hyderabad Joining Timeline: Immediate to 15 Days (strict) Key Responsibilities: Develop and optimize standard cell layouts. Perform physical verification and ensure DRC / LVS clean designs. Collaborate with circuit designers and CAD teams. Solve layout issues related to area, performance, and power. Mandatory Skills: Standard cell layout Cadence Virtuoso (Layout L / XL) Physical verification (Mentor Calibre) Knowledge of Electro-Migration, Latch-UP, Coupling, Crosstalk, IR – Drop, Parasitic Analysis, Matching, Shielding Good to Have: Skill coding / layout automation Experience in advanced nodes (e.g., 28nm and below) Strong problem-solving and communication skills Show more Show less

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Ampere is seeking a highly skilled and experienced candidate with proven expertise in PHY hardening, particularly in DDR and SerDes, with a focus on digital implementation and convergence. We are looking for a self-motivated individual with a proven track record in hardening state-of-the-art PHYs and contributing to the development of cutting-edge expertise. What You’ll Achieve As a PHY Hardening Engineer, you will collaborate with architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. This is an exceptional opportunity to showcase your engineering skills in a dynamic, fast-paced environment that fosters innovation and operates at the forefront of technology. High-Speed Digital Design Develop high-speed digital layouts, including DDR and other high-speed interfaces. Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits. Optimize layouts to minimize signal integrity issues, reduce power consumption, and meet timing, power, and manufacturability requirements. Coordinate with PHY vendors for hardening activities and deliverables. Estimate effort and timelines for PHY hardening tasks and provide feedback on timing/PDV. Chip-Level Physical Design Perform chip-level tasks such as floor planning, partitioning, and power/clock distribution. Handle chip assembly and ensure seamless integration of multiple IP blocks into the top-level design. Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC). Collaborate with the packaging team to refine bump placement and package routing considerations. Signal and Power Integrity Familiarity with signal and power integrity concepts in high-performance memory systems. Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation. Perform thermal and power integrity analysis to ensure reliable designs. Knowledge of advanced packaging techniques and considerations, an added plus Design-for-Test (DFT) Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms. Contribute to DFT-based timing closure activities. About You Bachelor's degree & 8 years of related experience or Master's degree & 6 years of related experience Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits Experience developing high-speed digital layouts, including DDR and other high-speed interfaces Handling chip assembly and ensure seamless integration of multiple IP blocks into the top-level design Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC) Worked with architects and RTL teams to develop physical constraints and optimize their design Integrate PHYs, controllers, and memory stacks into the top-level design Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs Handle micro-bump design to ensure proper alignment and minimize resistance Understand the SIPI impacts of bump placement Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms Strong communication and articulation skills are required to excel in this role What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER Full Chip Low Power Design and Signoff Engineer Overview WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities MTS SILICON DESIGN ENGINEER ( Full Chip Low Power Design & Signoff Engineer ) The Role As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. The Person A successful candidate should have minimum 8 to 15 years approximate work experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Key Responsiblities Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff Must have good understanding of RDL & Power grid design. Must know the NPV Static, Dynamic & SEM Run. Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis. Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff Should have good knowledge of package level EMIR analysis. Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. Should have good knowledge on simulation of special cell’s with target power analysis. Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA. Mentor/coach/guide design engineers to achieve the project goal. Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX Preferred Experience Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience with RHSC, PTPX, ICC2, Fusion Compiler Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR) Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc, Academic Credentials Bachelors or Master's degree in Computer/Electronics/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74461 Job Description Architects, designs and verifies circuits, logic, systems, algorithms, etc. to meet product requirements Determine design approaches and parameters Develops innovative new designs for patenting or protecting as trade secret Demonstrates good judgment in solving a broad range of issues, based on an advanced understanding of industry practices and company policies and procedures Responsible for custom layout, including overseeing the work of layout designers Reports on design results through design reviews, in accordance with company quality requirements and resolves action items generated as a result of these reviews Attends design reviews to provide input and learn from other designers’ experiences Research design techniques through technical publications and seminars Supports marketing in product definition Having a wide-ranging experience uses professional concepts and company objectives to resolve complex issues in creative and effective way Determines methods and procedures on new assignments and may coordinate the activities of other personnel Job Requirements A technology-related master’s degree or equivalent training and 8 or more years of analog/mixed-signal design experience developing mixed-signal ICs Proven leadership in analog/mixed signal design projects Strong knowledge of engineering fundamentals Advanced knowledge of CMOS fabrication processes Advanced knowledge of MOS transistors and analog/digital circuit design Knowledge of complex AD/DC analysis (poles, zeros, compensation) Advanced signal analysis knowledge Basic understanding of CMOS and BCD parasitic junctions and the risks associated with them Strong parasitic analysis knowledge (capacitance, resistance, power grid) Advanced knowledge of circuit building blocks (e.g., OPAMP, gm-C filters, switch capacitors, ADC, DAC, state-machines, and bus interfaces) Advanced design skills in system modeling Strong knowledge of UNIX, Matlab, and circuit simulation tools Proficiency in layout verification, DRC, LVS Additional skills (one or more of these are highly desirable) Working knowledge of device physics Working knowledge of digital design and design flows System knowledge (e.g., High Performance PLLs) Knowledge of scripting language (python, shell, skill) Advanced laboratory measurement skills (analog, digital) Knowledge of MS Office documentation, spreadsheet, presentation tools or equivalent tools Excellent written and verbal presentation skills Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Description Invent the future with us. Recognized byFast Company’s 2023 100 Best Workplaces for Innovators List,Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Ampere is seeking a highly skilled and experienced candidate with proven expertise in PHY hardening, particularly in DDR and SerDes, with a focus on digital implementation and convergence. We are looking for a self-motivated individual with a proven track record in hardening state-of-the-art PHYs and contributing to the development of cutting-edge expertise. What You’ll Achieve As a PHY Hardening Engineer, you will collaborate with architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. This is an exceptional opportunity to showcase your engineering skills in a dynamic, fast-paced environment that fosters innovation and operates at the forefront of technology. High-Speed Digital Design Develop high-speed digital layouts, including DDR and other high-speed interfaces. Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits. Optimize layouts to minimize signal integrity issues, reduce power consumption, and meet timing, power, and manufacturability requirements. Coordinate with PHY vendors for hardening activities and deliverables. Estimate effort and timelines for PHY hardening tasks and provide feedback on timing/PDV. Chip-Level Physical Design Perform chip-level tasks such as floor planning, partitioning, and power/clock distribution. Handle chip assembly and ensure seamless integration of multiple IP blocks into the top-level design. Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC). Collaborate with the packaging team to refine bump placement and package routing considerations. Signal and Power Integrity Familiarity with signal and power integrity concepts in high-performance memory systems. Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation. Perform thermal and power integrity analysis to ensure reliable designs. Knowledge of advanced packaging techniques and considerations, an added plus Design-for-Test (DFT) Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms. Contribute to DFT-based timing closure activities. About You Bachelor's degree & 8 years of related experience or Master's degree & 6 years of related experience Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits Experience developing high-speed digital layouts, including DDR and other high-speed interfaces Handling chip assembly and ensure seamless integration of multiple IP blocks into the top-level design Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC) Worked with architects and RTL teams to develop physical constraints and optimize their design Integrate PHYs, controllers, and memory stacks into the top-level design Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs Handle micro-bump design to ensure proper alignment and minimize resistance Understand the SIPI impacts of bump placement Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms Strong communication and articulation skills are required to excel in this role What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits includingcrechereimbursement, as well as a retirement plan,so thatyou can feel secure in your health,financial futureand child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : You will be part of ACE India , in the P- Core design team driving Intels latest CPUs in the latest process technology. In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in PNR from RTL to GDSII. Your responsibilities will include but not limited to:Meet the design targets of high performance and low-power digital design.Static timing analysis.Power Optimization.Design Convergence Experience at IP, SoC level.Ability to work in a highly dynamic environment across geographies.Back end design and implementation of new features.7Post silicon performance push activities. Qualifications: You must possess a Masters Degree in Electrical or Computer Engineering with atleast 6 or more years of experience in related field or a Bachelors Degree with at least 8 years of experience. Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS) . Preferred Qualifications- Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting. Strong verbal and written communication skills Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Qualifications: B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience with end-to-end SD flow - synthesis to GDS using industry standard EDA tool, with a proven track record of successful projects. Has good understanding on timing methodology, constraints building etc. Experience in floorplaning concepts and actual work, and integration of hierarchical design Good understanding and experience with multiple power domains designs. Have hands on experience on LV flow and clean up. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Description The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS, etc. Requirements 3-8years of experience in ASIC Physical Design Have good knowledge of the entire physical design process from floorplan to GDSII generation Good Exposure to Physical Verification Process Have hands-on experience in the latest sub-micron technologies below 10 nm Hands–on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Show more Show less

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Scribe Product Owner (SPO) you will serve as a technical and execution interface for partners and customers of the Scribe Design Team across a global structure. In this role you will help manage the MOI Scribe Product Owner(SPO) team and work with partners/customers to define requirements and drive completion of deliverables for given part type schedules. You will work with Process, Integration, Manufacturing, and Design teams across the company. You will use processes and metrics to improve the effectiveness and efficiency of the team. Specific Responsibilities Include But Not Limited To Be the primary interface to partners and customers for the scribe design team for communication of the product. Be accountable for ensuring scribe design work for each new DID or revision meets requirements, standards, and schedules. Work with other functional groups in Scribe Design Team to ensure that projects are adequately resourced, and requests are clearly understood and completed per schedule. Set up a system of processes to establish work flow in a globally distributed organization. Standardize BKM's across technologies and scribe design sites. Drive continuous improvement of tools and processes as well as eliminating redundant ones. Establish training, organize supporting material, and drive implementation across internal groups and external partners. Establish metrics to drive effectiveness and efficiency. Drive decisions through data, metrics, and processes. Qualifications Successful candidates for this position will have: Strong oral and written communication skills. Strong project management & Program management skills. Strong organizational and people management skills. Demonstrated innovative problem-solving skills. Good team building skills locally and globally. The ability to be flexible with travel and work hours to work within a global team. Understanding of device characterization, and relation of test structure layout to measurement results. Layout and Verification skills in Cadence and Calibre(DRC, LVS, Net extraction…). Understanding of device designs and the impact of parasitic components. Knowledge of general semiconductor mask procurement processes. Education & Experience Requirements BS degree in science or engineering or equivalent experience is required. 12+ years in an engineering position with management experience required. Experience with Scribe TEG design, Layout, and Verification and TEG design business process About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. Show more Show less

Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. Experience in PnR tools like ICC/Innovus with regards to physical convergence must. Good understanding of PD flows and overall backend tool flow would be beneficial. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and DRV. TCL/PERL Scripting is plus. Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable. Interested candidates can share their resumes to shubhanshi@incise.in

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. CAD Staff Engineer Our vision is to transform how the world uses information to enrich life. Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we create helps make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. Job Description As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities And Tasks Include, But Not Limited To Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. Proactively identify problem areas for improvement, propose, and develop innovative solutions. Develop methodologies for highly reliable layout with faster Time to Market approach. Continuously evaluate and implement new tools and technologies to improve the current layout development flows. Provide guidance and mentorship to junior members of the team. Qualifications 8+ years of experience in Layout automation, Physical Verification, or related domains. Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity. Working experience in Place and Router flows for custom memory layouts with industry standard tools like Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools etc. Working experience in PDN analysis tools like Totem/VoltusXFA/XA is preferable. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues is plus. Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC-Extraction, ESD, and Latch-up. Good understanding of programming fundamentals, as well as exposure to various programming languages including Skill (Cadence), Perl, Python, Tcl. Working knowledge of Linux is a must. Excellent problem-solving skills with attention to detail. Ability to work in a dynamic environment. Proficiency in working effectively with global teams and stakeholders. Education A bachelor’s or a master’s degree in Electronics, Electrical or Computer Engineering. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. Show more Show less

The candidate will be responsible for implementing the place and route of design blocks including floor planning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block level physical design closure in terms of timing, power, DRC/LVS etc. REQUIREMENTS: 4-9 years of experience in ASIC Physical Design Have good Hands on entire physical design process from floorplan till GDS generation Good Exposure to Physical Verification Process Have hands-on experience in latest sub-micron technologies below 7nm Hands –on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision Location :: Hyderabad & Bangalore *Adds on advantage atleast one or two projects has worked in AMD projects in his / her carier. Thanks, P Mohankrishna, Mohankrishna.p@Altcognitosystems.com Show more Show less