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Design Verification Engineer ACL Digital

3.0 - 5.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Design Verification Experience : 3-5 years Location : Bangalore Following skill set is required: Candidate must have GLS hands on experience in ZD/PAGLS/SDF/Scan dump verification. Strong Debug, UVM, System Verilog and Digital Fundamentals Should be able to debug Netlist functional failure. Low Power Awar verification. Timing Simulation failure, setup and hold violation fundamentals. Scan dump verification. Understanding Specs and Standards and developing relevant test plans. Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved. Good understanding of DDR families (LP/PC) and g...

Posted 21 hours ago

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