15.0 - 19.0 years

0 Lacs

karnataka

On-site

MIPS is looking for a highly experienced and motivated Engineering Manager to lead the CPU team. In this critical role, you will manage a team of skilled engineers dedicated to developing high-performance CPU cores based on the RISC-V architecture. Your responsibilities will include overseeing the entire RTL design lifecycle, ensuring technical excellence, innovation, and timely delivery. You will lead and mentor a team of microarchitecture and RTL design engineers focused on high-performance CPU core development. Your role will involve driving the design execution of CPU subsystems, meeting performance, power, area, and quality goals. You will be responsible for creating and refining microa...

Posted 1 month ago

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Analog Circuit Design Engineer SILCOSYS Solutions Pvt. Ltd.

3.0 - 7.0 years

0 Lacs

pune, maharashtra

On-site

As an Analog Design Engineer at Silcosys Solutions Private Limited, you will be part of a pioneering team dedicated to delivering cutting-edge analog design solutions that drive the future of technology. With a minimum of 3 years of experience in the semiconductor industry, this role offers exciting challenges and opportunities to contribute to groundbreaking projects. Your responsibilities will include collaborating with multidisciplinary teams to seamlessly integrate analog blocks into semiconductor products. You will design, simulate, and validate analog circuits, focusing on components such as PLLs, LDOs, Bandgap references, and High-Speed IO circuits. Detailed analysis, optimization, an...

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STA/ Synthesis - Engineer Qualcomm

1.0 - 5.0 years

0 Lacs

chennai, tamil nadu

On-site

Qualcomm India Private Limited is looking for a passionate STA and Synthesis Engineer to join their Engineering Group in Chennai. As an integral part of the cross-functional engineering teams, you will be engaged in all phases of design and development cycles, specifically focusing on Synthesis, Static Timing Analysis, and LEC of SoC/Cores. Your responsibilities will include full chip and block level timing closure, IO budgeting for blocks, logical equivalence checks between RTL to Netlist and Netlist to Netlist, as well as implementing low-power techniques such as clock gating, power gating, and MV designs. Additionally, you will be involved in ECO timing flow and should be proficient in sc...

Posted 2 months ago

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