Physical Design Engineer, Sr/Lead/Staff Qualcomm

4.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As an experienced Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design of ASICs, ensuring successful execution from netlist to GDS2. Your expertise in ASIC designs Place and Route flow, low-power methodologies, and PnR tools like Innovus/Fusion compiler will be crucial in this role. Your ability to debug Congestion and CTS issues, as well as familiarity with Sign-off methodology and tools, will be essential for ensuring the quality of the final product. Key Responsibilities: - Thorough knowledge and hands-on experience in ASIC designs Place and Route flow and methodology - Execute complete PD ownership from netlist to GDS2, including HM level P...

Posted 1 month ago

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Synthesis & STA Engineers Adroitec Systems

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a Synthesis & STA engineer, you will be responsible for performing RTL Synthesis to optimize the Performance/Power/Area of the designs. Your role will involve DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and Validation. You will be expected to create Power Intent for the designs, verify power intent on RTL, run static Low-Power checks on gate level netlists, and ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates. Collaborating with the Design/DFT/PD teams, you will set up signoff Static Timing Analysis and ECO flows to achieve timing closure. Additionally, you will be involved in Power Analysis, estimating power a...

Posted 3 months ago

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Physical Design Engineer, Sr/Lead/Staff Qualcomm

4.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design aspects of ASICs, including Place and Route (PnR) flow and methodology. Your key responsibilities will include: - Executing complete PD ownership from netlist to GDS2, encompassing HM level PV, LEC, low-power checks, PDN, and STA closure - Implementing Voltage Islands and low power methodologies, flows, and implementation - Debugging Congestion and Clock Tree Synthesis (CTS) issues - Utilizing PnR tools such as Innovus/Fusion compiler and flow - Familiarity with Sign-off methodologies and tools (PV/PDN/STA/FV/CLP/Scan-DRC(tk)) - Enhancing existing methodologies and flows - Proficiency in...

Posted 3 months ago

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