121 Logic Design Jobs - Page 2

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up

- Lead the architecture, design and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise - 10 to 15 years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design - Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements. - Follow agile project leadership principles. Work with the team on estimation and execution plan. - Ability to quickly understand issues spanning multiple functional domains, switch context frequently and provide solutions to problems, is necessary. Preferred technical and professional experience Bachelors / Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Expertise in logic synthesis, conformal, static timing analysis and Place and Route (PnR) Hands on experience in all aspects of the chip development process Experience in creating or improving low power synthesis methodologies Experience with scripting languages like Perl, Tcl or Python Floorplan, Place and Route at block level, physical design verification, LVS, DRC, IR drop analysis; netlist to gds at block level RTL logic design or implementation experience on multi-million gate ASICs will be a plus Strong communication skills to effectively communicate across all internal groups Description: As a synthesis, PnR Engineer, you will have responsibilities spanning various aspects of SOC design and implementation. Responsible for activities like Synthesis, LEC, Conformal, P&R etc. You will be working closely on methodology for improving synthesis QOR. Responsible for floor planning, placement and routing at block level. Will need to work closely with other engineers that are members of the RTL, STA and Physical Design teams. Education & Experience: BS or MS in EE, EECS, or CS is required 4+ years relevant work experience

Expertise in logic synthesis, conformal, static timing analysis and Place and Route (PnR) Hands on experience in all aspects of the chip development process Experience in creating or improving low power synthesis methodologies Experience with scripting languages like Perl, Tcl or Python Floorplan, Place and Route at block level, physical design verification, LVS, DRC, IR drop analysis; netlist to gds at block level RTL logic design or implementation experience on multi-million gate ASICs will be a plus Strong communication skills to effectively communicate across all internal groups Description: As a synthesis, PnR Engineer, you will have responsibilities spanning various aspects of SOC design and implementation. Responsible for activities like Synthesis, LEC, Conformal, P&R etc. You will be working closely on methodology for improving synthesis QOR. Responsible for floor planning, placement and routing at block level. Will need to work closely with other engineers that are members of the RTL, STA and Physical Design teams. Education & Experience: BS or MS in EE, EECS, or CS is required 4+ years relevant work experience

As a Hardware at , you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today s market. Your role and responsibilities As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design - Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up ABOUT BUSINESS UNIT

Develops high-quality, reliable, and efficient hardware designs for medical devices, including analog, digital, and mixed-signal circuits. Collaborates with cross-functional teams to ensure successful integration of designs into medical products. Participates in the development of new products, from concept to production. Ensures successful integration of electrical design with mechanical and software elements of the system. Provides technical guidance and mentorship to junior engineers. Develops, modifies, and approves electrical design documentation, specifications, and drawings. Supervises/coordinates an engineer and/or technicians on assigned work. Defines design requirements and hardware specifications based on customer or user requirements. Contributes to the development and documentation of electronic system architectures. Conducts design reviews, trade-off analyses, and risk assessments to ensure the optimal design solution is selected for each project. Leads the creation of designs of electronic circuit schematics for microcontroller-based systems and microprocessor-based systems, meeting performance objectives. Analyzes circuits using calculation and simulation methods to assess performance limits, effects of environmental and load stress, and timing interfaces to ensure consistent performance in safety-critical applications. Stays up to date with industry trends, emerging technologies, and regulatory requirements to maintain a competitive edge. Contributes to the development of design verification and validation plans, as well as executing tests to ensure design compliance with specifications. Defines appropriate test methods to verify designs meet their performance requirements. Completes deliverables related to design of systems and sub-systems of the overall electrical architecture. Collaborate with suppliers and external partners to source components and ensure component reliability and availability. Participates in the transfer of design knowledge and intellectual property to manufacturing teams to ensure successful production ramp-up. Contributes to the continuous improvement of design processes, tools, and methodologies to improve efficiency and quality. Directs the layout of circuit assemblies to meet emissions and immunity performance requirements and design for manufacturability guidelines. Executes protocols and testing required to validate the safety and effectiveness of the design(s). Leads the troubleshooting and problem-solving efforts related to electrical aspects of devices and associated systems. Creates and communicates design/test plans, tasks, deliverables, and status. Manages time and resources to meet committed schedule milestones.) Qualifications A Bachelor's or Master's degree in Electrical or Electronics Engineering or a related field is required, with a minimum of 11 years of experience in electro-mechanical medical device product design, with knowledge of infusion pumps medical devices being an added advantage. A strong foundation in digital electronics, including logic design, digital circuits, and computer architecture. Proficiency in digital logic design, timing analysis, AC & DC analysis, and familiarity with simulation tools such as VHDL, Verilog, and Cadence is an added advantage. Strong knowledge of digital circuit design, digital system architecture, and design methodologies using microcontrollers, microprocessors, System on Module (SOM), CPLD, FPGAs, and ASICs. Knowledge of digital components, such as logic gates, flip-flops, memory technologies (such as SRAM, DRAM, and flash memory), digital signal processing, and communication protocols (such as I2C, SPI, USB, and Ethernet). Familiarity with Ethernet physical layers, such as RJ45, twisted pair, and fiber optics, and networking hardware, such as switches, routers, and hubs. Knowledge of Wi-Fi networking hardware, such as access points, routers, and client devices, and understanding of Wi-Fi network topologies, Wi-Fi testing and troubleshooting tools, and methodologies. Understanding of Wi-Fi power management and quality of service (QoS) mechanisms. Familiarity with Ethernet network management tools, such as SNMP and NetFlow, and Wi-Fi protocols, including TCP/IP, UDP, and ICMP. Understanding of Ethernet power over data (PoE) and power over Ethernet plus (PoE+) technologies. Knowledge of industry standards and regulations, such as TIA/EIA and ETSI, to ensure compliance with network performance and safety requirements. Familiarity with PCB layout and design for manufacturability (DFM) principles. Knowledge and experience using CAD systems for printed circuit board schematic design and layout (preferably Altium Designer). Understanding of signal integrity and power integrity concepts to ensure reliable performance of circuits. Experience with measurement and testing equipment to verify circuit performance. Experience with design automation tools, such as LabVIEW, Cadence Virtuoso, AWR Design Environment, or MATLAB. Strong problem-solving skills and the ability to work independently and collaboratively. Excellent communication skills, both written and verbal, with the ability to effectively communicate complex technical concepts to non-technical stakeholders. Strong organizational skills and the ability to manage multiple projects simultaneously. Experience with regulatory requirements, such as FDA 510(k) and IEC 60601, is a plus. Familiarity with agile development methodologies and the ability to work in a fast-paced, dynamic environment and adapt to changing priorities.

Job Details: : Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block. Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE. Qualifications: B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 7+ years of DFT experience Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. - Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) - Hands on experience of different Branch Prediction techniques - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Knowledge of at least one object oriented or functional programming language and scripting language. - Nice to haves - Knowledge of instruction decode and handling pipeline hazards - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Master's Degree/PhD

Responsibilities: * Candidate responsible for SPM programming as per required sequence. * Candidate also required to visit at site to provide programming work related support.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of Processors or ASICs. Minimum 3+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Multi-processor cache coherency, Memory subsystem, IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Preferred technical and professional experience Verify the different functions/components in a PCI Express Controller & high speed SERDES (PHY). Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug Formal verification experience

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Software E-plan/Autocad, Solid Work, Solid Edge Knowledge on General/Busbar arrangement+design Design of Modular/bolted/Switchgear panels Design calculations/control/operation logic + VFD +PLC Relevant IS/IEC Handling team, Client & multiple projects Required Candidate profile BE/Dip. in Elect. Skill E plan, Autocad 8-12 yrs. in Switchgear panel designing If required needs to travel for client discussions/Drawing approval Knows Tech. Elect/Mech. related to Switchgear design

SENIOR LOGIC DESIGN ENGINEER Fortune 100 Organization Location: Bangalore Title Logic Design Engineer Your Role and Responsibilities As a Logic Design Engineer, you will play a pivotal role in the end-to-end development of features with significant impact on our Mainframe and/or Power customers. From conceptualization to validation, you will be responsible for developing features, presenting proposed architectures, estimating efforts, and collaborating across various teams to ensure successful implementation. Your primary responsibilities include: Feature Development and Architecture: Develop features and propose architectures in high-level design discussions, ensuring alignment with project goals and customer requirements. Effort Estimation: Estimate the overall effort required for feature development, providing valuable input to project planning and scheduling. Cross-Functional Collaboration: Collaborate with verification, physical design, test generation, and mill code teams to develop features, fostering cross-functional teamwork and synergy. Pre-Silicon Design Sign-off: Sign off on design during the pre-silicon phase, ensuring readiness for tape-out and fabrication. Post-Silicon Validation: Validate hardware functionality post-silicon, conducting thorough testing to ensure feature integrity and performance. Required Technical and Professional Expertise Microarchitecture and Logic Design: 7 to 12 years of experience in microarchitecture and logic design, demonstrating proficiency in designing complex digital systems. VLSI Design in VHDL/Verilog: Experience with VLSI design using hardware description languages such as VHDL or Verilog, enabling efficient implementation of digital logic. Processor Architecture Understanding: Good understanding of processor architectures, including RISC and CISC, facilitating the development of features tailored to specific processor requirements. Designer Simulations: Experience in developing and performing designer simulations, ensuring functionality and performance goals are met prior to silicon realization. Design Closure and Verification Coverage: Proven ability to drive design closure, including test plan reviews and verification coverage analysis, ensuring comprehensive validation of designs. Preferred Technical and Professional Experience Power-Efficient Logic Design: Experience in designing power-efficient logic, optimizing designs for low power consumption without sacrificing performance. Physical Design and Timing Constraints: Understanding of physical design concepts and timing constraints, facilitating seamless integration with physical implementation and timing closure processes. Python Scripting: Proficiency in Python scripting, enabling automation of design tasks and enhancing productivity in design workflows. Preferred Education Master's Degree Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

locationsIndia, Bangalore time typeFull time posted onPosted 18 Days Ago job requisition idJR0271803 Job Details: About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.Tech/M.Tech +6 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Have experience working in GPU/CPU domain. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

We are seeking a skilled SoC (System on Chip) Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be working on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires deep knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required ToolsSynopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation. Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Summary This position is open for 2-10 years experience candidate in Qualcomm CSI (Custom/SemiCustom implementation) team Candidate will be part of CSI team working on RTL- GDS HM implementations using custom flow and methodology for custom design . Qualcomm is one of the fastest growing semiconductor organization in India making high-end Chips with the most advanced technologies. To support its growing needs, we have strong CSI team for the design, development of various highspeed and low power IPs being used in SoC. Individual has to work on RTL-GDS implementation. This will involve innovating new solutions in close collaboration with the other design teams. Job Responsibilities Job responsibilities include design and development of custom macro using Schematic design at block level (Ex RegArray, memory subsystem) Frontend verification and model generations CLP/PAGLS/LEC verifications at block level. Functional verification using spice/gatesim. Timing Signoff using PT, Candidate should be able to collaborate with different teams. Skillset/Experience 2-10 year of experience: Strong knowledge in transistor circuit design& block level logic design of Memory subsystem & Data path. STA for the design to close Set-up, Hold, MPW, Transition, etc Design verification using ESPCV & LEC, Simulation using Finesim & HSPICE. Front-end RTL Design (Verilog RTL design, System Verilog, Synopsys Design Compiler, Cadence RTL Compiler, LEC, PLDRC, Static Timing Analysis and PTPX) Physical Design using industry-standard RTL2GDS flow including Synopsys ICC2, Cadence Encounter. Scripting in Perl/Python/Shell/Tcl for productivity is a plus IP development (custom macro transistor level design, physical integration, collateral generation, flow development) and PPA quantification. Interface with Process Technology Team to understand the complex DRC and DFM requirements of the advanced technology nodes Work with cross functional teams (Architecture, Test/Verification , Product, CAD, Layout, Physical Design) to gather/define/implement specs Transistor level implementation of the block using CMOS/Domino/Cell-Based/Data path styles Implement power/clock gating techniques, Implement power/clock gating techniques, Implement industry standard as well as custom DFT techniques Implement clock distribution using custom/CTS techniques for low skew/latency/power, Implement block layout using custom/compiler techniques using custom/semi-custom/stdcell libraries Implement block level floor planning using custom and/or tiling techniques Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must . Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must . Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required . Hands on experience in Multi Clock designs, Asynchronous interface is a must . Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Your Role and Responsibilities As a Logic Design Engineer, you will play a pivotal role in the end-to-end development of features with significant impact on our Mainframe and/or Power customers. From conceptualization to validation, you will be responsible for developing features, presenting proposed architectures, estimating efforts, and collaborating across various teams to ensure successful implementation. Your primary responsibilities include: Feature Development and Architecture: Develop features and propose architectures in high- level design discussions, ensuring alignment with project goals and customer requirements. Effort Estimation: Estimate the overall effort required for feature development, providing valuable input to project planning and scheduling. Cross-Functional Collaboration: Collaborate with verification, physical design, test generation, and mill code teams to develop features, fostering cross-functional teamwork and synergy. Pre-Silicon Design Sign-off: Sign off on design during the pre-silicon phase, ensuring eadiness for tape-out and fabrication. Post-Silicon Validation: Validate hardware functionality post-silicon, conducting thorough testing to ensure feature integrity and performance. Required Technical and Professional Expertise Microarchitecture and Logic Design: 3 to 8 years of experience in microarchitecture and logic design, demonstrating proficiency in designing complex digital systems. VLSI Design in VHDL/Verilog: Experience with VLSI design using hardware description languages such as VHDL or Verilog, enabling efficient implementation of digital logic. Processor Architecture Understanding: Good understanding of processor architectures, including RISC and CISC, facilitating the development of features tailored to specific processor requirements. Designer Simulations: Experience in developing and performing designer simulations, ensuring functionality and performance goals are met prior to silicon realization. Design Closure and Verification Coverage: Proven ability to drive design closure, including test plan reviews and verification coverage analysis, ensuring comprehensive validation of designs. Preferred Technical and Professional Experience Power-Efficient Logic Design: Experience in designing power-efficient logic, optimizing designs for low power consumption without sacrificing performance. Physical Design and Timing Constraints: Understanding of physical design concepts and timing constraints, facilitating seamless integration with physical implementation and timing closure processes. Python Scripting: Proficiency in Python scripting, enabling automation of design tasks and enhancing productivity in design workflows.

Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon RTL Design Engineer :- • Job Description o As a member of Design(RTL) team, you will be responsible for the microarchitecture and design of IPs/Controllers for SoC/SiP designs. o Perform architectural/design trade-offs for required product features, performance and system constraints. o Responsible for defining and documenting design specifications. o Develop and deliver a fully verified RTL to achieve the design targets and quality sign-off requirements. o Design and Implement logic functions that enable efficient test and debug. o Provide Debug support for design verification and post-silicon activities. • Skill and Experience Requirements: o Minimum 7 + years industry experience with Masters degree (preferred) or Bachelors degree in Electrical or Computer Engineering. o Hand-on experience with micro-architecture and RTL development (System Verilog) for x86/ARM CPU Processors or high-speed custom ASICs/Accelerators with focus on any one: Cache controller, IO interfaces (PCIe, CXL, Ethernet), UCIe, Memory controllers, Display, Video encoding/transcoding. o Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis and sign-off quality flows. o Self-starter with strong interpersonal and communication skills . o Excellent team player. .

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelor's degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience. Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs Core DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl Proficient in Unix/Linux environments Strong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT) Strong understanding of software development methodologies Experience in leading and managing software development projects Knowledge of technologies and tools used in software development Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT) This position is based at our Chennai office A 15 years full time education is required Qualification 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NA Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelor's degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience. Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs Core DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl Proficient in Unix/Linux environments Strong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT) Strong understanding of software development methodologies Experience in leading and managing software development projects Knowledge of technologies and tools used in software development Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT) This position is based at our Chennai office A 15 years full time education is required Qualification 15 years full time education