407 Lint Jobs - Page 8

1. RTL development and Verification for Digital subsystems, Memory Subsystems including BIST. 2. DFT Insertion and Verification signoff for IO, ARM-PNR, Memory Digital Subsystems with Tessent/Embedded MBIST 3. MBIST, ATPG, RSQ Verification and sign-off. 4. Formal verification, Cross Clock Domain checks, Power/Timing sign off 5. Verify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suit Independently. Skillset: 1. Hands on Experience with RTL, Synthesis, 2. Hands on experience in defining ICC/Synthesis constraints that meets timing closure needs 3. Familiarity with DFT flows includes MBIST, ATPG, RSQ and Verification methodologies and best practices for the...

What You''ll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for ...

We are looking for a skilled SAP CDC Business Analyst (Technical) with 4 to 6 years of experience. The position is based in [location to be specified]. Roles and Responsibility Collaborate with cross-functional teams to analyze business requirements and develop solutions using SAP CDC. Design, implement, and maintain technical documentation for SAP CDC projects. Provide technical support and training to end-users on SAP CDC applications. Develop and maintain reports, dashboards, and other visualizations using SAP CDC tools. Work closely with stakeholders to identify and prioritize project requirements. Ensure compliance with industry standards and best practices in SAP CDC implementation. Jo...

Role Overview: You will be responsible for independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will own tasks related to RTL Design/Module and provide support and guidance to engineers in various areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your role will involve anticipating, diagnosing, and resolving problems while coordinating with cross-functional teams to ensure on-time quality delivery approved by the project manager and client. Additionally, you will be expected to automate design tasks flows, write scri...

Role Overview: You will be responsible for ASIC RTL design with 10+ years of experience and proficiency in Verilog/System Verilog. Your role will involve working with multiple clock and power domains, integrating and validating various MIPI cores, debugging, and implementing CSI/DSI controllers. Additionally, you will be creating micro-architecture specifications, reviewing vendor IP integration guidelines, running integrity check tools, and participating in design verification and physical implementation processes. Key Responsibilities: - Possess 10+ years of ASIC RTL Design experience and proficiency in Verilog/System Verilog - Work with multiple clock and power domains - Integrate and val...

As a MERN Stack Developer at Xcelore, you will play a crucial role in the development and maintenance of robust web applications using the MERN stack (MongoDB, Express.js, React.js, Node.js, typescript). Your responsibilities will include: - Collaborating with multifunctional teams to design, code, and deploy scalable solutions. - Integrating backend services using your knowledge of RESTful APIs. - Crafting responsive UI components with React.js to ensure exceptional user experiences. - Utilizing Node.js for efficient server-side development. - Conducting Unit Testing using Jest and end-to-end testing using Cypress. - Maintaining code quality through linting, husky, and prettier. - Employing...

As a Principal Digital Engineer, WLAN MAC at Synaptics, you will be responsible for defining WiFi MAC architecture, technically leading the team on design methodologies, optimizing designs for power and area targets, guiding the team through digital design, RTL implementation, and various checks for chip productization. You will collaborate with different teams, including Systems/SW team, DV team, and design/product evaluation team, to ensure successful product development. **Key Responsibilities:** - Define WiFi MAC architecture based on the Standard - Lead the team technically on design methodologies - Optimize designs to meet power and area targets - Guide the team through various design ...

You have a rewarding opportunity at Qualcomm India Private Limited in the Engineering Group, specifically in the Hardware Engineering team. As a Senior SoC Design Engineer, you will play a crucial role with your extensive experience in SoC design and expertise in various protocols and architectures. Let's delve deeper into the responsibilities and qualifications required for this role: **Role Overview:** - Utilize your 15+ years of experience in SoC design to contribute effectively to the team - Demonstrate proficiency in AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking/reset/debug architecture - Showcase your knowledge of peripherals like USB, PCIE, and SDCC - Gain an under...

We are looking for a skilled ASIC / RTL Design Professional with 7 to 15 years of experience. The ideal candidate will have expertise in RTL, Coding, Design, IP Design, SOC Development, Lint, CDC, and Micro Architecture. Roles and Responsibility Design and develop high-quality ASICs using RTL design principles. Collaborate with cross-functional teams to ensure successful project execution. Develop and implement coding standards for efficient code generation. Participate in IP design and SOC development activities. Troubleshoot and debug issues related to Lint, CDC, and Micro Architecture. Ensure compliance with industry standards and best practices. Job Requirements Strong knowledge of RTL, ...

The primary focus at EITSI is to develop the next generation LIMS (Lab Information Management system), Customer portals, e-commerce solutions, ERP/CRM system, Mobile Apps & other B2B platforms for various Eurofins Laboratories and businesses. POSITION NAME QA/Sr. QA Automation Test ENGINEER POSITION TITLE (ENGLISH): QA/Sr. QA Automation Test ENGINEER REPORTING TO: MANAGER REPORTING LOCATION BANGALORE WORKING LOCATION BANGALORE NUMBER OF FTEs UNDER RESPONSIBILITY: 0 SUMMARY OF POSITION AND OBJECTIVES Smart quality analyst required to work as an automation test engineer to deliver high quality product, by speeding up end to end test cycles. POSITION & OBJECTIVES : Job description EVOLUTION Wha...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

The Client DDRPHY team is looking for an energetic and passionate Logic Design Engineer who will work on high-speed digital design targeted towards low power optimized IP implementations. You will be responsible for overseeing definition, design, verification and your responsibilities will include but are not limited to - defining architecture and microarchitecture features of the block being designed, implementing RTL in System Verilog, setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to he...

Develop and maintain formal equivalence checking flows using Synopsys Formality. Collaborate with cross-functional teams to align verification methodology with design goals. Implement and support Formality ECO flows for incremental synthesis. Drive methodology improvements for SoC design verification. Coordinate with internal stakeholders and external vendors to deliver high-quality solutions. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSI Design. 5–8 years of hands-on experience with Synopsys Formality or similar tools (e.g., Cadence Con...

Role & responsibilities Please share me interested candidate cv galeiah.g@honeybeetechsolutions.com Position Name RTL Engineer Position type: Permanent Total Exp: 5+ years HBTS Budget: Open Notice Period: Immediate 15DAYS Work Location: Hyderabad Job Description Must have: 1. At least 5yrs of industry experience 2. Experience with RTL frontend tools like RDC, CDC, Lint etc 3. Experience with writing and validating synthesis constraints. 4. Experience with scripting like perl, python, tcl etc. Preferred candidate profile

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineering professional with a passion for tackling complex SoC challenges. With 12+ years experience, you thrive in dynamic environments and excel at leading multidisciplinary teams through the intricacies of RTL design and signoff. You possess deep expertise ...

As a Senior ASIC CAD/EDA Engineer in the VLSI/Semiconductor Industry, your role involves deploying and supporting front-end tools, developing scripts for automation, working closely with design, implementation, and verification teams. You will be responsible for: - Deploying and supporting front-end tools like RTL simulators, low power tools, static RTL checkers, and formal verification tools - Developing scripts to automate regression and debug flows, enabling CI/CD - Streamlining compute infrastructure utilization using load distribution tools - Identifying and prioritizing internal user needs and developing capabilities for them - Integrating tools, repos, and compute infrastructure using...

You have 8-12 years of experience in SoC/IP Design. Your expertise lies in writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem, and SoC level integration. You are also proficient in RTL Development, following Coding Standards, and utilizing tools like Lint, CDC tools for Verification, and Debugging of test cases. Additionally, you excel in code and functional coverage analysis. Your knowledge encompasses Clocking Methodology and Low Power Implementation. You have hands-on experience in writing constraints and exceptions, performing Synthesis, Timing Analysis, and Design for Test Implementation. Moreover, you have experience in power partitioning and usage of CPF/UPF....

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner) Candidate will be responsible for RTL design for integration of IO pads into So...

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / s...

Roles and Responsibilities: 1. Handling request from vessel or TSI for Adding / amending /removal of PMS routines: Amendment request from vessel is sent to TSIs approval and as technical committee member same will be forwarded to PMS DB (by referring technical manuals, makers manual, makers circular). Activation of calendar-based work order while new job is added. For counter-based work order liaising with vessel and activating the same. on completion making sure amendments are reflecting in shore end as requested and intimating the same to vessel /TSI. 2. On signers briefing: For newly joining officers briefing on Shippalm v3 for all 5 modules provide on daily basis via MS teams and physica...

We Are:. At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.. You Are:. You are a seasoned engineering professional with a passion for tackling complex SoC challenges. With 12+ years' experience, you thrive in dynamic environments and excel at leading multidisciplinary teams through the intricacies of RTL design and signoff. You possess deep expert...

Key Responsibilities: Develop, integrate, and validate RTL designs for complex ASIC/SoC projects. Perform lint checks, CDC analysis, and RDC verification using industry-standard tools (Spyglass, Meridian, etc.). Collaborate with design verification teams to ensure functional correctness and quality sign-off. Drive synthesis-friendly RTL coding practices and participate in design reviews. Debug and resolve issues across RTL, lint, CDC, and timing. Work closely with architecture and verification teams for spec-to-RTL implementation . Required Skills & Expertise: 5+ years of experience in ASIC RTL design & verification . Strong hands-on expertise in Lint, CDC, and Meridian tools. Proficiency in...

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Pe...

Role Overview: As a member of our dynamic team, you will contribute to the development of custom silicon solutions that drive the future of Google's direct-to-consumer products. Your role will be pivotal in innovating products that are globally cherished, influencing the next wave of hardware experiences to deliver exceptional performance, efficiency, and integration. You will work towards Google's mission of organizing the world's information and making it universally accessible and useful, synergizing the best of Google AI, Software, and Hardware to craft profoundly beneficial experiences. The team is dedicated to researching, designing, and advancing new technologies and hardware to enhan...

Meta is hiring talented individuals to join our Infrastructure organization as ASIC Frontend Implementation Engineers (RDC/CDC). In this role, you will play a critical part in designing and developing efficient System on Chip (SoC) and IP for data center applications.As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize your expertise in RTL Lint, CDC analysis, timing constraints, and synthesis to ensure seamless integration of various components to build efficient System on Chip (SoC) and IP for data center applications.By joining our te...