201 Lint Jobs - Page 6

• Design Methodology, Micro-architecture, RTL. • Work with the architecture team to develop the uArch & Subsequently write RTL. • Develop Design Methodology, starting with the machine learning architecture. • Synthesis, STA, Equivalence checking. Required Candidate profile * EXP in SOC design methodology, Micro-architecture, Emulation & back-end DEV., & Chip Bring-up. * EXP in Developing ARM CPU based SoCs, Network-on-Chip & interfaces such as MIPI-CSI, Ethernet & PCIe

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic ...

Android Lead Responsibilities : 1. Responsible for robust and efficient implementation 2. Suggest technical solutions for short and long term 3. Candidate will be able to build and integrate android libraries and modules 4. Candidates will be able to design, build, and maintain high performance, reusable, and reliable Android/Java code. Responsible for robust and efficient implementation 5. Candidate will be able to debug skills and ability to solve issues of subordinates 6. Must ensure the best possible performance, quality, and responsiveness of the application, identify and correct bottlenecks and fix bugs. 7. Design and develop high-quality code. 8. Participate and lead software design m...

1+ Yrs Experience working on modern front-end web technologies, including: React, JS(ES6+) TypeScript, Next.js, HTML5, CSS3 and Less/Sass ability to write mixins, partials, functions, etc developing highly-optimized applications using React and Redux Required Candidate profile Experience interning in the E-Commerce Experience with the standard tooling Webpack, Babel, Linting, JS Typing, and Prettier. Experience in Caching

Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures

3+Yrs Exp.Android device platform, Proficient In Kotlin Language knowledge of design patterns like MVP, MMVM, RxJava, and others knowledge of Android SDK, NDK, Android Studio, Gradle, and Lint Knowledge of Flutter or React native will be an advantage Required Candidate profile Candidate will be able to build and integrate android libraries and modules and design-build and maintain high performance reusable java and OOPS concept

8+Yrs Exp.Android device platform, Proficient In Kotlin Language knowledge of design patterns like MVP, MMVM, RxJava, and others knowledge of Android SDK, NDK, Android Studio, Gradle, and Lint Knowledge of Flutter or React native will be an advantage Candidate will be able to build and integrate android libraries and modules and design-build and maintain high performance reusable java and OOPS concept

Responsibilities : 1. Responsible for robust and efficient implementation 2. Suggest technical solutions for short and long term 3. Candidate will be able to build and integrate android libraries and modules 4. Candidates will be able to design, build, and maintain high performance, reusable, and reliable Android/Java code. Responsible for robust and efficient implementation 5. Candidate will be able to debug skills and ability to solve issues of subordinates 6. Must ensure the best possible performance, quality, and responsiveness of the application, identify and correct bottlenecks and fix bugs. 7. Design and develop high-quality code. 8. Participate and lead software design meetings and a...

Java Developer (Eng Open IDM)JD: Work as a Java-Forgerock Engineer (openAM / openIDM) for DSP project. Develop, test, deliver and support features and the platform. To be successful in this role, you should meet the following requirements(Must have ) Strong knowledge of object oriented ( OOPS ) & SOLID principles Hands on experience with Java, Maven & Springboot. Must have very good problem solving and coding skills. Good knowledge with dependency injection frameworks, spring-security, oauth, authentication and authorization Must have working knowledge of developing enterprise Java applications. Hands on experience on Java security, memory management and threading mechanism and maintaining c...

Responsibilities: Should have good understanding of SoC design flow Hands-on expertise in writing RTL in Verilog and System Verilog (optional VHDL) language, SoC level RTL integration ,Linting, CDC checks, STA ,constraints, UPF

hiring for RTL design Lead, for Hyderabad location , Exp - 8+ yrs RTL Design, SOC integration, CDC / Lint, IP Enhancement. Interested, kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources f...

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / s...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Function Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience 5-10 years with Masters (6 to 10 years with Bachelors) Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for...

A passion for high quality software engineering and technology. Thorough understanding of React and its core principles; proficiency in JavaScript, including DOM manipulation and the JavaScript object model Developing new user-facing features and reusable components using latest web technology. Translating designs and wireframes into high quality clean, scalable code. Optimizing components for maximum performance across a vast array of web-capable devices and browsers Proficient understanding of web markup, including JavaScript, HTML5, CSS3, Tailwind, MUI, SCSS, Bootstrap Proficient in defining and implementing a scalable architecture that ensures separation of concern between components, AP...

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. S...

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5...

Job Description Hand-on experience and Comprehensive knowledge of Static Timing Analysis. Hands-on experience in Logical aware Synthesis, Logical Equivalence check and, Static Timing analysis. Hands-on the DMSA flow to fix pre and post STA timing. Knowledge in the Timing closure on Sub-system level & Block level and Chip level. Knowledge in writing Manual ECOs to fix timing violations and DRCs. Knowledge of constraint development. Good Knowledge of TCL scripting and UNIX env. Leading the team of 4 to 5 team members by guiding and mentoring on the STA /Synthesis. Pre-layout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closu...

Proven experience as a Full Stack Developer with a focus on both front-end and back-end technologies with min 4+yrs experience Strong Technical Hands-on experience in Node.js, MongoDB, Angular 8+ , and ExpressJS projects In-depth knowledge of front-end technologies such as HTML, CSS, and JavaScript frameworks (e.g. Angular) Familiarity with SAfe/Agile methodologies and software development best practices Experience with cloud services and infrastructure (AWS,) Good understanding of database technologies, such as SQL/ NoSQL /MongoDB.etc Confident and autonomous while developing, testing, and deploying robust solutions that are fast, scalable, and responsive. Ability to work in a dynamic envir...

Job Description: We are looking for a Senior RTL Design Engineer with solid experience in ASIC Digital Design . The ideal candidate should possess strong expertise in RTL design using Verilog/System Verilog , with a proven background in developing complex digital designs and working on high-speed interfaces. This is a pure design-focused role ; candidates with FPGA-centric experience will not be considered . Key Responsibilities: Develop and implement RTL designs using Verilog/System Verilog . Work on SoC and IP-level designs focused on high-speed interfaces (e.g., APB, AXI, AHB, DDR, PCIe). Perform lint , CDC , RDC checks and validate timing constraints. Support post-silicon validation . Us...

HI Greetings for the day!!1 I am hiring for TOP MNC for VLSI Design Engineer, check the attached JD for more clarity, kindly revert with below details ON swati@thinkpeople.in Total Experience Rel Exp Current CTC Exp ctc Location Notice period Current org primary skill ; Skills : PD / DV / AMS / DFT / ASIC OR RTL Design: (please mention) JD; Analog Circuit Design Lead : TitleMandatory Skills Experience : 7+ years Responsibilities :1. Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization.2. Must have led the entire Analog IP development cycle and team.3. Circuit Design implementation of IPs including LDOs, Band Gap reference, Curren...

• 3+ years of solid experience in IP/SoC design • Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts • Good knowledge of Digital Design and RTL development • Hands-on experience with SoC Design, Verilog RTL coding • Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug • Working knowledge of Lint, CDC, PLDRC, CLP etc • Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification • Manage SoC dependencies, planning and tracking of all front-end design related tasks • Working for successful design delivery...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 15+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interfac...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interfac...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a VLSI engineers who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version manage...