318 Lint Jobs - Page 5

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineering professional with a passion for tackling complex SoC challenges. With 12+ years experience, you thrive in dynamic environments and excel at leading multidisciplinary teams through the intricacies of RTL design and signoff. You possess deep expertise ...

As a Senior ASIC CAD/EDA Engineer in the VLSI/Semiconductor Industry, your role involves deploying and supporting front-end tools, developing scripts for automation, working closely with design, implementation, and verification teams. You will be responsible for: - Deploying and supporting front-end tools like RTL simulators, low power tools, static RTL checkers, and formal verification tools - Developing scripts to automate regression and debug flows, enabling CI/CD - Streamlining compute infrastructure utilization using load distribution tools - Identifying and prioritizing internal user needs and developing capabilities for them - Integrating tools, repos, and compute infrastructure using...

You have 8-12 years of experience in SoC/IP Design. Your expertise lies in writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem, and SoC level integration. You are also proficient in RTL Development, following Coding Standards, and utilizing tools like Lint, CDC tools for Verification, and Debugging of test cases. Additionally, you excel in code and functional coverage analysis. Your knowledge encompasses Clocking Methodology and Low Power Implementation. You have hands-on experience in writing constraints and exceptions, performing Synthesis, Timing Analysis, and Design for Test Implementation. Moreover, you have experience in power partitioning and usage of CPF/UPF....

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner) Candidate will be responsible for RTL design for integration of IO pads into So...

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / s...

Roles and Responsibilities: 1. Handling request from vessel or TSI for Adding / amending /removal of PMS routines: Amendment request from vessel is sent to TSIs approval and as technical committee member same will be forwarded to PMS DB (by referring technical manuals, makers manual, makers circular). Activation of calendar-based work order while new job is added. For counter-based work order liaising with vessel and activating the same. on completion making sure amendments are reflecting in shore end as requested and intimating the same to vessel /TSI. 2. On signers briefing: For newly joining officers briefing on Shippalm v3 for all 5 modules provide on daily basis via MS teams and physica...

We Are:. At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.. You Are:. You are a seasoned engineering professional with a passion for tackling complex SoC challenges. With 12+ years' experience, you thrive in dynamic environments and excel at leading multidisciplinary teams through the intricacies of RTL design and signoff. You possess deep expert...

Key Responsibilities: Develop, integrate, and validate RTL designs for complex ASIC/SoC projects. Perform lint checks, CDC analysis, and RDC verification using industry-standard tools (Spyglass, Meridian, etc.). Collaborate with design verification teams to ensure functional correctness and quality sign-off. Drive synthesis-friendly RTL coding practices and participate in design reviews. Debug and resolve issues across RTL, lint, CDC, and timing. Work closely with architecture and verification teams for spec-to-RTL implementation . Required Skills & Expertise: 5+ years of experience in ASIC RTL design & verification . Strong hands-on expertise in Lint, CDC, and Meridian tools. Proficiency in...

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Pe...

Role Overview: As a member of our dynamic team, you will contribute to the development of custom silicon solutions that drive the future of Google's direct-to-consumer products. Your role will be pivotal in innovating products that are globally cherished, influencing the next wave of hardware experiences to deliver exceptional performance, efficiency, and integration. You will work towards Google's mission of organizing the world's information and making it universally accessible and useful, synergizing the best of Google AI, Software, and Hardware to craft profoundly beneficial experiences. The team is dedicated to researching, designing, and advancing new technologies and hardware to enhan...

Meta is hiring talented individuals to join our Infrastructure organization as ASIC Frontend Implementation Engineers (RDC/CDC). In this role, you will play a critical part in designing and developing efficient System on Chip (SoC) and IP for data center applications.As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize your expertise in RTL Lint, CDC analysis, timing constraints, and synthesis to ensure seamless integration of various components to build efficient System on Chip (SoC) and IP for data center applications.By joining our te...

Work with system architects to understand the functional and performance requirements of a unit or feature. Define micro-architecture and develop RTL for owned unit and/or feature. Work with verification and physical design teams to ensure that the unit or feature is accurately verified and implemented. Own silicon bring-up in conjunction with post silicon validation and SW teams. Mentor junior engineers and guide them in their work. What we need to see: BS / MS or equivalent experience. 2+ years of experience. Proven knowledge in implementation of complex features or units. Expertise in micro architecture definition, RTL coding using Verilog or System Verilog. Expertise in using design and ...

Hiring: SoC Design Implementation Engineer | Bangalore Location: Bangalore | Experience: 4 30 Years | Immediate to 15 Days Joiners Only ACL Digital is hiring SoC Design Implementation Engineers for a customer-urgent requirement . If you are passionate about SoC design, CDC/RDC verification, and synthesis, this is your chance to work on cutting-edge semiconductor technologies. Key Responsibilities Drive Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis for complex SoCs. Perform debug and root-cause analysis of CDC/RDC issues in collaboration with RTL and DV teams. Own RTL synthesis, constraint development (SDC), and optimization for area, power, and timing. Collaborate with...

NOTE- Looking for more than 7+ yrs of experience only. Job Description for RTL We are hiring a SoC Integration Engineer with strong expertise in RTL coding and SoC integration flows. The ideal candidate should have hands-on experience with SpyGlass Lint, CDC, DC Synthesis, and VCLSP, along with scripting knowledge. Key Responsibilities: Integrate IP blocks into SoC at RTL level Perform RTL coding and micro-architecture design (Verilog/VHDL) Run and debug SpyGlass Lint, CDC, and DC Synthesis flows Conduct STA and design rule checks Develop automation scripts (Perl, Python, Shell, Tcl) Collaborate with verification and physical design teams Work on VCLSP and SoC-level integration flows Primary...

As a member of the team working on custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. **Key Responsibilities:** - Collaborate with architects to develop microarchitecture - Perform Verilog/SystemVerilog RTL coding - Conduct functional/performance simulation debugging - Carry out Lint/CDC/FV/UPF checks - Participate in test planning and coverage analysis - Develop RTL implementations meeting power, performance, and area goals - Be involved in ...

Job Specs : Expertise in ASIC RTL Design Expertise in ASIC IP Design Expertise in CDC and Lint tools Expertise in design and simulation tools Expertise in Video processing algorithms / interfaces Expertise in CXL / PCIe Protocol, 5G, Datacenter Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations Preferred resources with valid regional work permit.

We are looking for a passionate and experienced EDA Methodology Engineer to join our ASICdesign team, focusing on Spyglass lint checking using Synopsys Spyglass for CDC/RDC. In this role, you’ll work closely with design teams and EDA vendors to develop and implement robust verification flows that ensure structural correctness across design stages Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSIDesign. 5–8 years of hands-on experience with Synopsys Spyglass. Strong understanding of RTL design languages: VHDL, Verilog, SystemVerilog. Expertis...

Skills Strong proficiency of Javascript and DOM manipulation Experience with Typescript on ReactJS development Experience with reusable component development using React functional components Have a sharp understanding on the best practice approach to leverage the data management in ReactJS Have a sharp understanding on the best practice approach to leverage lifecycle management in ReactJS Familiarity with the atomic design pattern to build reusable component Experience with Story Book to document the components and its properties Experience with the ReactJS code quality standard (Unit Test, Sonar, Lint) to determine the quality gate Experience with CSS/SCSS/SAAS and responsive design implem...

Expertise in ASIC RTL Design Expertise in ASIC IP Design Expertise in CDC and Lint tools Expertise in design and simulation tools Expertise in Video processing algorithms / interfaces Expertise in CXL / PCIe Protocol, 5G, Datacenter

1+ Yrs Experience working on modern front-end web technologies, including: React, JS(ES6+) TypeScript, Next.js, HTML5, CSS3 and Less/Sass ability to write mixins, partials, functions, etcdeveloping highly-optimized applications using React and ReduxR

Responsibilities : 1. Responsible for robust and efficient implementation 2. Suggest technical solutions for short and long term 3. Candidate will be able to build and integrate android libraries and modules

As an experienced ASIC RTL Design Engineer at MarvyLogic, you will be responsible for designing cutting-edge solutions that impact various industries. Your role will involve working with multiple clock and power domains, integrating and validating MIPI cores, debugging, and implementing CSI/DSI controllers. Your expertise in Verilog/System Verilog will be crucial in creating micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance with coding standards. Additionally, you will play a key role in the design verification and physical implementation processes to meet performance goals. **Key Responsibilities:** - Utiliz...

8+Yrs Exp.Android device platform, Proficient In Kotlin Language knowledge of design patterns like MVP, MMVM, RxJava, and others knowledge of Android SDK, NDK, Android Studio, Gradle, and Lint

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

3+Yrs Exp.Android device platform, Proficient In Kotlin Language knowledge of design patterns like MVP, MMVM, RxJava, and others knowledge of Android SDK, NDK, Android Studio, Gradle, and Lint