201 Lint Jobs - Page 2

You should have a minimum of 12 years of experience in ASIC design, with proficiency in Verilog coding, RTL design, and creating complex control path and data path designs. It is essential to have knowledge of interface Protocols such as UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, and SATA. Familiarity with RTL checks including LINT, SDC, CDC, synthesis flow, LEC, and timing constraints is required. Experience in writing Verilog testbench and conducting simulations will be beneficial. At Cadence, we are seeking individuals who are passionate about technology and innovation. Join us in making a significant impact on the world of technology. Let's work together to solve challenges tha...

We are seeking an ASIC RTL Design Lead to join our team in Hyderabad at the earliest. The ideal candidate should possess over 10 years of experience and demonstrate expertise in the following areas: - Proficiency in RTL Design utilizing verilog - Experience in SoC and Subsystem integration, including the integration of peripherals such as PCIE, Ethernet, and USB - Ability to conduct front end flow environment bringup - Strong understanding of Flows, Lint, CDC, Synthesis, Formality, VCLP - Knowledge of tcl or perl scripting - Development of CDC and synthesis constraints, Timing analysis, Signoff If you meet these requirements and are interested in this opportunity, please send your profile to...

As a skilled professional with a Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience, along with 6 years of expertise in ARM-based System on a chip (SoCs), interconnects, and Application-Specific Integrated Circuit (ASIC) methodology, you are well-equipped to take on the responsibilities of this role. Additionally, your 5 years of experience in Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture, coupled with your proficiency in a coding language like Python or Perl, make you an ideal candidate for this position. Ideally, you hold a Master's degree or a PhD in Electrical Engineering, Computer Science, or possess equiv...

You will be part of a highly skilled and challenging high-speed parallel PHY design team, working on interfaces such as DDR, LPDDR, etc. Your responsibilities will include designing and developing high-speed interface PHY and its sub-blocks, such as high-speed data paths, analog calibration, training, IP initialization, low power control, test, loopback, etc. You will be accountable for various aspects of design and verification from specification to silicon, as well as interface design for the controller and SoC. Your role will also involve active participation in problem-solving and implementing opportunities for improvement. Additionally, you will mentor and coach other design team member...

The ideal candidate for this position should have a minimum of 3 to 5 years of experience and possess strong core front-end skills including HTML5 (plus APIs), CSS3, JavaScript, and Responsive Web Development. Proficiency in CSS3 Pre-Processors like LESS or SASS, OOJS, and JavaScript Design Patterns is required. Experience in ES6 and using Babel Transpiler, as well as familiarity with MVC/MV- frameworks & libraries such as Angular, Ember, React or Vue, is essential. Proficiency in Version Control System, like Git, Web Services integration using AJAX, and knowledge of concepts like REST are also key requirements. Additionally, candidates should have experience with Code Quality Tools like LIN...

You should have experience in Logic design and RTL coding, as well as SoC design and integration for complex SoCs. Proficiency in Verilog/System-Verilog and Multi Clock designs including Asynchronous interfaces is essential. Familiarity with ASIC development tools such as Lint and CDC is required. Knowledge of Synthesis and understanding of timing concepts is a plus. Experience with ECO fixes, formal verification, and AMBA protocols like AXI, AHB, and APB, along with SoC clocking/reset architecture is necessary. Strong communication skills, proactive attitude, creativity, curiosity, motivation to learn, and good collaboration skills are expected. Your responsibilities will include understand...

Job Description for RTL We are hiring a SoC Integration Engineer with strong expertise in RTL coding and SoC integration flows. The ideal candidate should have hands-on experience with SpyGlass Lint, CDC, DC Synthesis, and VCLSP, along with scripting knowledge. Key Responsibilities: Integrate IP blocks into SoC at RTL level Perform RTL coding and micro-architecture design (Verilog/VHDL) Run and debug SpyGlass Lint, CDC, and DC Synthesis flows Conduct STA and design rule checks Develop automation scripts (Perl, Python, Shell, Tcl) Collaborate with verification and physical design teams Work on VCLSP and SoC-level integration flows Primary Skills: RTL Design: Verilog, VHDL, Micro-architecture ...

RTL Design Engineer 4+yrs experience Location: Hyderabad_onsite Malayasia Advanced RTL Design and DFT trainee, looking forward to build a career in the VLSI domain. To work with full determination and dedication, to achieve organization as well as personal goals. Skills : Verilog, Design for Testability (DFT), RTL Coding, STA, System Verilog, C, FPGA design Hands-on experience : Router 1x3 - Design using Verilog, RISCV32I Processor- RTL Design and DFT

As a member of the team at this organization, you will play a crucial role in the development of custom silicon solutions that will drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process that leads to the creation of products that are beloved by millions around the globe. Your expertise will be key in shaping the next generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, and a minimum of 3 years of experience in Register-Transfer Leve...

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. S...

Job Description for RTL We are hiring a SoC Integration Engineer with strong expertise in RTL coding and SoC integration flows. The ideal candidate should have hands-on experience with SpyGlass Lint, CDC, DC Synthesis, and VCLSP, along with scripting knowledge. Key Responsibilities: Integrate IP blocks into SoC at RTL level Perform RTL coding and micro-architecture design (Verilog/VHDL) Run and debug SpyGlass Lint, CDC, and DC Synthesis flows Conduct STA and design rule checks Develop automation scripts (Perl, Python, Shell, Tcl) Collaborate with verification and physical design teams Work on VCLSP and SoC-level integration flows Primary Skills: RTL Design: Verilog, VHDL, Micro-architecture ...

You will be responsible for executing internal projects or small tasks within customer projects related to VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. Your role will involve working as an Individual contributor on tasks such as RTL Design, Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will be expected to analyze and complete assigned tasks within the defined domain successfully and on time with minimal support from senior engineers, ensuring quality delivery as approved by the senior engineer or project lead. Quality of deliverables is a key focus, requiring clean delivery of modules that are easy to...

As a candidate for this role, you should hold a Bachelor's degree in Electrical/Computer Engineering or possess equivalent practical experience. You should also have at least 2 years of experience working with RTL design using Verilog/System Verilog and microarchitecture, particularly in the realm of ARM-based SoCs, interconnects, and ASIC methodology. A Master's degree in Electrical/Computer Engineering would be considered a preferred qualification for this position. Additionally, experience with methodologies for RTL quality checks (such as Lint, CDC, RDC) and low power estimation, timing closure, and synthesis would be beneficial. Join a dynamic team that is dedicated to pushing boundarie...

We are seeking highly motivated, energetic, and team-oriented individual contributors who can work on synthesis, LEC, and constraints for NXPs digital IPs, working in close collaboration with the RTL team. Key Responsibilities Work closely with the architects and RTL team on synthesis, LEC, and constraints of NXP digital IPs Carry out floor planning, and physically aware synthesis on high-performance IPs Perform timing and power analysis on the design database (db), improve the recipe, and provide timing feedback to the RTL team Leads or solo owners are expected to work with minimal micro-management needs. They should be able to communicate with other project members to manage task divisions...

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for l...

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for l...

The primary focus at EITSI is to develop the next generation LIMS (Lab Information Management system), Customer portals, e-commerce solutions, ERP/CRM system, Mobile Apps & other B2B platforms for various Eurofins Laboratories and businesses. POSITION NAME QA/Sr. QA Automation Test ENGINEER POSITION TITLE (ENGLISH): QA/Sr. QA Automation Test ENGINEER REPORTING TO: MANAGER REPORTING LOCATION BANGALORE WORKING LOCATION BANGALORE NUMBER OF FTEs UNDER RESPONSIBILITY: 0 SUMMARY OF POSITION AND OBJECTIVES Smart quality analyst required to work as an automation test engineer to deliver high quality product, by speeding up end to end test cycles. POSITION & OBJECTIVES : Job description EVOLUTION Wha...

We are looking for a skilled RTL Design Engineer with 3 to 7 years of experience to join our team at Capgemini Technology Services India Limited. The ideal candidate will have a strong background in IT Services & Consulting and be proficient in RTL design. Roles and Responsibility Design and develop high-quality RTL code for various projects. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop and maintain technical documentation for RTL designs. Troubleshoot and debug issues related to RTL code. Participate in code reviews and ensure adherence to coding standards. Stay updated with industry trends and emerging technologies in RTL design. Job Requ...

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5...

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: At least 5yrs of industry experience Experience with RTL front-end tools like RDC, CDC, Lint etc. Experience with writing and validating synthesis constraints. Experience with scripting like Perl, python, TCL etc. Experience Required: 5 + Years TekWissen Group is an equal opportunity employer supporting workforce diversity.

The people are the culture. We encourage a culture of passion for technology solutions that impact businesses. We also make sure that our people pursue their individual passions. Working with us means you get an in-depth understanding of a range of industries and emerging technologies that help us build solutions that are futuristic and impactful. More importantly, the experience of being at MarvyLogic may help you evolve as a person toward enjoying a more fulfilling life. Minimum BE/BS degree in Electrical/Electronics/Computer science required. At least 5-10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts. Experience in physic...

You have an immediate job opening with one of your valuable clients in Hyderabad for FPGA with Firmware profiles. The ideal candidate should have at least 8 years of experience in FPGA, RTL Design, RTL Coding, Firmware, CDC, and Lint. The location for this position is Hyderabad and the notice period is immediate to 15 days. If you are interested in this opportunity, kindly share your updated profile with Anand Arumugam at anand.arumugam@modernchipsolutions.com or call +919900927620 for further discussion.,

The ASIC/SOC Front End Design Engineer role involves setting up ASIC QA flows for RTL design quality checks, understanding top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. You will be responsible for executing various design steps such as Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP. Additionally, you will create clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers while reviewing flow errors, design errors, and violations. As an ASIC/SOC Front End Design Engineer, you will debug CDC and RDC issues, provide RTL fixes, and support the DFX team for DFX controller integration, Scan insertion...

You should have a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture, or equivalent practical experience. With 4 years of experience in RTL coding and experience with RTL quality checks methodologies such as Lint, CDC, RDC. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a specialization in computer architecture is preferred. Experience in implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs like Display or Video Codecs would be advantageous. Also, familiarity with ASIC design methodologies for clock domai...

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in usi...