407 Lint Jobs - Page 11

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: At least 5yrs of industry experience Experience with RTL front-end tools like RDC, CDC, Lint etc. Experience with writing and validating synthesis constraints. Experience with scripting like Perl, python, TCL etc. Experience Required: 5 + Years TekWissen Group is an equal opportunity employer supporting workforce diversity.

The people are the culture. We encourage a culture of passion for technology solutions that impact businesses. We also make sure that our people pursue their individual passions. Working with us means you get an in-depth understanding of a range of industries and emerging technologies that help us build solutions that are futuristic and impactful. More importantly, the experience of being at MarvyLogic may help you evolve as a person toward enjoying a more fulfilling life. Minimum BE/BS degree in Electrical/Electronics/Computer science required. At least 5-10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts. Experience in physic...

You have an immediate job opening with one of your valuable clients in Hyderabad for FPGA with Firmware profiles. The ideal candidate should have at least 8 years of experience in FPGA, RTL Design, RTL Coding, Firmware, CDC, and Lint. The location for this position is Hyderabad and the notice period is immediate to 15 days. If you are interested in this opportunity, kindly share your updated profile with Anand Arumugam at anand.arumugam@modernchipsolutions.com or call +919900927620 for further discussion.,

The ASIC/SOC Front End Design Engineer role involves setting up ASIC QA flows for RTL design quality checks, understanding top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. You will be responsible for executing various design steps such as Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP. Additionally, you will create clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers while reviewing flow errors, design errors, and violations. As an ASIC/SOC Front End Design Engineer, you will debug CDC and RDC issues, provide RTL fixes, and support the DFX team for DFX controller integration, Scan insertion...

You should have a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture, or equivalent practical experience. With 4 years of experience in RTL coding and experience with RTL quality checks methodologies such as Lint, CDC, RDC. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a specialization in computer architecture is preferred. Experience in implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs like Display or Video Codecs would be advantageous. Also, familiarity with ASIC design methodologies for clock domai...

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in usi...

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation ...

You are a highly skilled and motivated Senior CAD Engineer responsible for supporting and enhancing the front-end EDA infrastructure. Your expertise in CAD tools, scripting, and ASIC design flows will be instrumental in developing efficient and scalable methodologies for large-scale silicon projects. Your key responsibilities will include deploying and supporting front-end EDA tools such as RTL simulators, static checkers, and formal verification tools. You will be required to develop automation scripts for regression and debug flows, administer and optimize Linux-based compute infrastructure, and collaborate with internal teams to identify CAD needs and deliver tailored solutions. Additiona...

You have an immediate job opening with one of our valuable clients in HYD locations for FPGA with Firmware profiles. The ideal candidate should have a minimum of 8 years of experience in FPGA, RTL Design, RTL Coding, Firmware, CDC, and Lint. The location for this position is in HYD with a notice period of immediate to 15 days. If you are interested in this opportunity, kindly share your updated profile with Anand Arumugam at anand.arumugam@modernchipsolutions.com or call at +919900927620 for further discussion.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions worldwide. Your expertise will play a crucial role in shaping the next generation of hardware experiences, focusing on delivering unparalleled performance, efficiency, and integration. In this role, you will lead a team of ASIC RTL engineers, overseeing sub-system and chip-level integration activities. Your responsibilities will include planning tasks, conducting code and design reviews, and developing complex features....

As an ASIC Design Engineer specializing in UPF and Low Power Design, you will be responsible for owning and driving RTL design for complex digital blocks with multiple power domains. Your role will involve defining, implementing, and validating power intent using UPF 2.0/3.0 for ASIC and SoC designs. Collaboration with verification and physical design teams will be crucial to ensure correct propagation and verification of power intent across the flow. You will work closely with architecture teams to define low power design strategies including power gating, clock gating, and multi-voltage domains. Additionally, analyzing and debugging power-related issues during RTL and gate-level simulation...

As an RTL Engineering Lead at Google, you will play a vital role in driving innovation and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will be instrumental in shaping the future of hardware experiences that cater to millions of users worldwide. By leveraging your expertise, you will enhance performance, efficiency, and integration in the next generation of Google products. With a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience, along with 6 years of hands-on experience in micro-architecture and coding, particularly in memory compression, interconnects, coherence, cache, Dynamic Random-Acces...

You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software tea...

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions to power Google's direct-to-consumer products. Your role will involve contributing to the innovation that drives the creation of products loved by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. Your responsibilities will include: - Contributing as an ASIC RTL engineer to sub-system and chip-level integration activities. This will involve task planning, conducting code and design reviews, and contributing to sub-system/chip-level integration. - Working closely with the architecture team to dev...

Job Title: Lead RTL Design Engineer Microarchitecture (10+ Years) Company: ACL Digital Experience: 10 to 15 Years Location: [Insert Location or Remote/Hybrid] Job Type: Full Time Contact Email: prabhu.p@acldigital.com Contact Number: +91-8754387484 Job Description: ACL Digital is hiring a Lead RTL Design Engineer with strong expertise in microarchitecture and RTL design . This is a leadership role ideal for professionals with 10+ years of experience in digital design, ASIC/SoC development, and hands-on RTL coding. Key Responsibilities: Own microarchitecture and RTL development of complex IPs or subsystems. Lead block-level design from spec to synthesis and signoff. Drive RTL design using Ver...

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. You...

You are invited to apply for the position of "ASIC RTL Engineer" at Semi Leaf consulting Service located in Bangalore. With 3-8 years of experience, if you are available to join within 30 days and prefer working in a WFO mode, this opportunity might be just for you. As an ASIC RTL Engineer at Semi Leaf, your responsibilities will include working on ASIC RTL design, RTL Logic Synthesis, LEC, Conformal, ECO, FC Check, and having proficiency in either TCL or Python. You must have Synthesis or Implementation experience, familiarity with the Linux environment, excellent communication skills, and experience with at least one serial protocol like UART, I2C, SPI. Skills with SOC Architecture, experi...

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System ...

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in PCIe IP...

Elhaa Technologies Pvt Ltd is currently seeking an Android Programmer to join our team in Coimbatore. As an Android Programmer, you will play a key role in developing mobile applications, maintaining and enhancing existing code, and working collaboratively with the team to deliver innovative solutions. To excel in this role, you should have a strong proficiency in Kotlin and Java, along with hands-on experience using Android Studio. Knowledge of Android SDK, Jetpack Components, and familiarity with Android Architecture Components like MVVM and MVP are essential. Experience with RESTful APIs, Retrofit, Google Play Services, and Firebase will be beneficial for integrating backend services and ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on e...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangal...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC desi...