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Principal Design Engineer Cadence

5.0 - 12.0 years

0 Lacs

bengaluru, karnataka, india

On-site

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Experience: 5- 12 years Location - Bangalore/Pune/Noida/Hyderabad Responsibilities Complete DFT ownership of projects including: Test architecture definition. Identifying and implementing RTL changes for DFT. Performing scan insertion, LEC checks, low power CLP checks. Developing timing constraints for test mode timing closure. Scan and ATPG for different fault models. Boundary scan, ACJTAG, IEEE 1500 implementation and verification. IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests. Running zero delay and timing simulations and debugging on all the above aspects....

Posted 1 day ago

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