6.0 - 8.0 years

25 - 40 Lacs

Bengaluru

Work from Office

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

Posted 5 months ago

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Senior Dft Engineer Cyient

4.0 - 8.0 years

15 - 30 Lacs

Hyderabad, Bengaluru

Work from Office

About the Role Senior DFT Engineer (4 - 8 Years) | Hyderabad / Bangalore, India Are you passionate about making complex SoCs more testable, robust, and production-ready? As a Senior DFT Engineer , youll play a hands-on role in implementing critical DFT features that ensure silicon success across next-generation ASICs. You will work alongside experienced leads on advanced nodes (14nm and below), contribute to DFT flow development, and implement key test strategies such as scan compression, MBIST, and JTAG. This is your chance to grow into a technical specialist while playing a central role in the silicon lifecyclefrom RTL to tape-out. Key Responsibilities Support DFT architecture implementati...

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DFT Experts - Technical Lead Newsoft Consultants

7 - 12 years

35 - 80 Lacs

Pune, Bengaluru, Hyderabad

Work from Office

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

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DFT Experts - Tech Lead NEWSOFT CONSULTANTS

7.0 - 12.0 years

35 - 80 Lacs

hyderabad/secunderabad, pune, bangalore/bengaluru

Hybrid

Posted Date not available

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Senior Engineer Sivaltech

5.0 - 10.0 years

17 - 27 Lacs

bengaluru

Work from Office

Role & responsibilities • Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis Proficiency in simulation debug with timing/SDF Experience with LBIST and Mixed Signal Radar ICs is highly desirable Ability to debug and root cause simulation failures Must be proactive, collaborative, and detail-oriented, capable of exercising independent judgment Preferred candidate profile Immediate joining

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