2.0 - 6.0 years

0 Lacs

karnataka

On-site

We are seeking a Digital/Memory Mask Design Engineer who is enthusiastic about joining a dynamic team of individuals tasked with managing complex high-speed digital memory circuit designs. At NVIDIA, we have a history of reinventing ourselves. Our creation of the GPU has driven the growth of the PC gaming industry, redefined modern computer graphics, and transformed parallel computing. Today, the field of artificial intelligence is rapidly expanding globally, necessitating highly scalable and massively parallel computational power in which NVIDIA GPUs excel. NVIDIA is a constantly evolving entity that thrives on seizing new opportunities that are uniquely challenging, can only be tackled by us, and hold significance for the world. Our mission is to enhance human creativity and intelligence. As a member of the NVIDIA team, you will be immersed in a diverse and supportive environment where everyone is encouraged to deliver their best work. Join our diverse team and discover how you can leave a lasting impact on the world! Your responsibilities will include: - Executing IC layout for innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes of 3nm, 5nm, 7nm, and lower nodes using industry-standard methodologies. - Leading the architecture and layout design of critical memory subsystems, such as control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes. - Overseeing custom layout and verification of complex memory cells, establishing standards and methodologies for compiler-driven design flows. - Managing and optimizing all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks. - Identifying and resolving intricate physical design issues in compiler-generated layouts, while mentoring junior engineers in established methodologies. - Providing expertise on IR drop and EM mitigation strategies, creating design methodologies for resilient memory layouts. - Demonstrating deep knowledge in ultra-deep sub-micron layout challenges, regularly introducing and implementing advanced solutions. - Developing memory compilers, leading problem-solving efforts, and driving optimization for performance, area, and manufacturability. - Fostering effective teamwork across cross-functional teams, influencing project direction and ensuring alignment with organizational goals. - Excelling in resource management, representing the team in technical discussions with customers. - The layout of IP will feature significant digital components. - Embracing and implementing the best layout practices/methodology for composing digital Memory layouts. - Adhering to company procedures and practices for IC layout activities. Desired qualifications: - B.E/B Tech. / M Tech in Electronics or equivalent experience with a minimum of 2 years" proven expertise in Memory layout in advanced CMOS processes. - Proficiency in industry-standard EDA tools for Cadence. - Experience in laying out high-performance memories of various types. - Knowledge of Layout fundamentals, including different bit cells, Decoders, LIO, etc. (matching devices, symmetrical layout, signal shielding). - Experience with floor planning, block-level routing, and macro-level assembly. - Profound understanding of top-level verification, including EM/IR quality checks, and detailed knowledge of layout-dependent effects such as LOD, Dummification, fills, etc. #LI-Hybrid,

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