Hiring for Senior C developer with 3-6 years of experience. Mandatory Skillset- C, C++, Python, Rtos, Jtag Candidate should have working experience in above mentioned skills.

Validation and Embedded Engineers Job Category: Validation Job Type: Full Time Job Location: Bangalore Camera and Display subsystem, Memory subsystem, Memory Management, ARM Architecture Capabilities and Experience: Bachelor s degree in Electrical Engineering or Computer Science with 5+ years of relevant experience, with minimum 3+ years in silicon validation Silicon Validation experience, developing stress test plans and content, silicon validation frameworks or related infrastructure, debugging skills. Experience in validating hardware features for SOC (display system, memory subsystem, memory management) Familiarity with ARM CPU Architecture Caching and Coherency protocols knowledge Performance Validation Experience Expertise in Security protocols and architecture e.g., IOMMU, Access control, Encryption etc. Firmware Development Strong knowledge of OS Fundamentals, Multi-threaded embedded programming Experience in Bare Metal testing. Validation experience of protocols using software on chip blocks, specifically camera, CSI PHY, ISP, display protocols DSI and DP Pre and Post Silicon SoC level expertise on data-chains, DMAs, fabric etc. Proficiency in JTAG Debugger languages- Lauterbach PRACTICE with experience of debugging complex systems and performance bottlenecks. Ability to measure various analog parameters in the lab with highspeed oscilloscopes and other lab equipment. Ability to write and execute memory related tests to establish functional health of our SoCs on silicon, both under normal and PVT conditions. Good understanding of validation fundamentals. Solid understanding of emulation technologies. Familiarity with emulators and waveform-based debugs. Programming Skills- Assembly, mixed assembly programming, C, C++ Scripting Python, shell scripting Microsoft excel tools for report generation /graphs. Responsiblities: Building emulation models, running, and debugging test cases, resolving environment issues, and driving emulation and acceleration capabilities for pre- and post- silicon validation in platforms like Synopsys Zebu or Cadence Palladium Drive report generation, analysis of memory margins across PVT Drive the post silicon bring up and validation activities for the DRAM. Execute the DRAM validation, margin data collection, stress testing across PVT. Team player and a mentor who is self-driven, motivated. Responsible for quality and timeliness of the team output

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. The engineer will contribute to the stability team in debugging Linux Kernel and System level issues for Qualcomm chipsets. The position requires -Excellent debug skills, especially in the core kernel software stability domain -Excellent knowledge of ARM architecture -Excellent knowledge of Linux kernel and the device driver model -Expert level knowledge of C -Prior experience with Android is a plus - Knowledge of debug tools such as JTAG -Master or bachelor"™s degree in ECE, EE or CS. - 1 to 4 years of relevant work experience

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Job description: The engineer will contribute to the stability team in debugging Linux Kernel and System level issues for Qualcomm chipsets. The position requires: Excellent debug skills, especially in the core kernel software stability domain Excellent knowledge of ARM v7 and v8 architecture, exception levels etc Excellent knowledge of Linux kernel and the device driver model Expert level knowledge of C Excellent communication and soft skills Prior experience with Android, system debug etc is a plus Knowledge of debug tools such as JTAG is a plus Master or bachelor"™s degree in ECE, EE or CS. Preferably 2 to 4 years of relevant work experience

Job Area: Engineering Services Group, Engineering Services Group > Support Engineering General Summary: As a Support Engineer at Qualcomm, you will significantly contribute to our product improvement and work with other Engineers to sustain aspects of our product development life cycle. Support Engineers will also play a critical role in resolving technical system issues that promote product reliability. You will have endless opportunities to learn and grow in the Engineering development space. Minimum Qualifications: Bachelor's degree and 1+ year of Support Engineering or related work experience. OR Associate's degree and 2+ years of Support Engineering or related work experience. OR High School Diploma or equivalent and 3+ years of Support Engineering or related work experience. *Completed advanced degree in a relevant field may be substituted for up to one year (Master"™s = one year) of work experience. You will be part of Qualcomm's Automotive Platform Systems Team in Bangalore, which is responsible for design, delivery and support of high-quality Chipset validation, integration and SW development platforms. In this role, the primary responsibility of the individual will be to work closely with platform design engineers in testing, troubleshooting, deploying, maintaining and supporting Qualcomm"™s Automotive platforms. Support tickets raised by users of these platforms will have to be resolved by the individual "“ either on their own or in collaboration with adjacent functions (HW Design/Manufacturing/Test/Prototype rework teams.) Individual may work on multiple tickets at any point of time, so, systematic tracking and updating of status is expected. The environment is fast-paced and requires cross-functional interaction daily. Good communication, planning and execution skills are a must. Following are the required skills and experience: - Ability to understand Schematics, component datasheets, BOM, Engineering Drawings- Ability to debug electronic HW systems, write board-level rework instructions and guide technicians to implement and verify rework- Ability to operate test equipment "“ power supplies, oscilloscopes and logic analyzers, protocol analyzers etc. - Working knowledge in Windows required - Knowledge of using JTAG debuggers preferred- Working knowledge in Unix is desirable - Experience in a support role and working with ticket tracking tools (like JIRA) desirable - Experience in running automated tests and ability to perform first-level debug in test / test-environment related issues is a strong plus - Strong individual contributor who will work well in a team environment - Good communication skills Qualifications: MinimumDiploma in Electrical/Electronics Engineering and 8+ years of experience in Electronic System Assembly, Test, Troubleshooting, lab support and system maintenance

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division) s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers. The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage. Experience with either Mentor Graphics DFT tools (TestKompress, Fastscan) or Synopsys DFT tools (DFTMax, Tetramax) is highly desirable. The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently and also supervise the work of other team members as required. The candidate should possess excellent communication skills. Educational qualification & Experience Level : Bachelor s degree with 8+ years of relevant experience or Master s degree with 6+ years of relevant experience Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 3 years of experience in architecture, microarchitecture, design, or physical design of low speed interfaces or GPIO. Experience in protocols such as Improved Inter-Integrated Circuit (I2C) , Universal Asynchronous Receiver-Transmitter (UART) , Serial Peripheral Interface (SPI). Preferred qualifications: Master's degree in Electrical Engineering or related field. Experience with the following protocols: Inter-IC Sound (I2S), Joint Test Action Group (JTAG), Time-Division Multiplexing (TDM), Persistent Data Masking (PDM), SoundWire, System Power Management Interface (SPMI). Experience in IO timing closure and with GPIO circuit design. Experience in Mobile Industry Processor Interface (MIPI) protocols like Improved Inter-Integrated Circuit (I3C), I2C, UART, and SPI. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Define the requirements and author architecture specifications and the programming guides. Analyze performance, power, area, and cost trade-offs. Perform Third-Party IP phones (3PIP) selection of low speed interface IPs and General Purpose input/output (GPIO) IPs. Define and maintain SoC input/output (IO) map collaborating with the system team. Lead and support throughout the life cycle of low speed interfaces development. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Dear Candidate, We are hiring a C++ Developer to work on high-performance systems, real-time applications, and embedded solutions. The role requires deep knowledge of C++ and system-level programming. Key Responsibilities: Write high-efficiency code in C++11/14/17 Design and develop low-latency applications Optimize software for memory and processing efficiency Debug and troubleshoot complex system behaviors Collaborate with hardware, firmware, and software teams Required Skills & Qualifications: Proficient in C++, STL, and multithreading Experience with memory management, pointers, and system calls Knowledge of Linux development, IPC, and embedded systems Familiar with GDB, Valgrind, and performance profiling tools Soft Skills: Strong troubleshooting and problem-solving skills. Ability to work independently and in a team. Excellent communication and documentation skills. Note: If interested, please share your updated resume and preferred time for a discussion. If shortlisted, our HR team will contact you. Kandi Srinivasa Reddy Delivery Manager Integra Technologies

Responsibilities: Perform Linux board bring-up on custom hardware platforms, including initialization and hardware validation. Develop, configure, and debug bootloaders (e.g., U-Boot) for embedded systems. Customize and maintain the Linux kernel , device trees, and low-level drivers for target hardware. Work with BIOS/UEFI firmware , supporting hardware initialization and system boot processes. Configure and troubleshoot Linux file systems (e.g., ext4, squashfs, NFS) for embedded environments. Program in C/C++ to develop and optimize embedded applications, device drivers, and low-level utilities. Analyze and resolve issues related to hardware-software integration and performance optimization. Collaborate with hardware, testing, and system architecture teams to ensure stable Linux deployments. Utilize tools like JTAG, oscilloscopes, and logic analyzers for debugging and validation. Maintain technical documentation, board bring-up guides, and contribute to knowledge-sharing. Good to Have: Experience with 64-bit Intel/ARM processors or NVIDIA platforms (Jetson, etc.) Familiarity with high-speed interfaces like PCIe, USB 3.x, HDMI, DisplayPort Exposure to Yocto or Buildroot for building custom Linux distributions Understanding of RTOS integration with Linux systems Knowledge of secure boot and trusted execution environments (TEE)

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. #LI-RP1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division) s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics It involves working with the Physical Design & STA team for DFT mode timing closure The role could also involve direct interaction with external customers The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug Strong problem solving & debugging skills are a must Expertise in scripting languages such as perl, shell, etc is an added advantage Experience with either Mentor Graphics DFT tools (TestKompress, Fastscan) or Synopsys DFT tools (DFTMax, Tetramax) is highly desirable The candidate should have worked with team across multiple geographies The candidate should be able to handle his/her work independently and also supervise the work of other team members as required The candidate should possess excellent communication skills Educational qualification & Experience Level : Bachelor s degree with 8+ years of relevant experience or Master s degree with 6+ years of relevant experience

We are looking for a Fellow-level Engineer to join our team to develop world-class DFT architecture for EPYC Server products. In this role you will be engaged with the SoC Architects, Micro Architects, PD Engineers, Product Engineers, etc, to define and implement the DFT Architecture, guide/technically lead the DFT Team to ensure right pre-si verification is done for the DFT logic, and the highest level of Scan coverage is achieved to hit the product goals. You will also be responsible for driving innovation to continuously improve the execution and also drive TTR (Test Time Reduction) THE PERSON: You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models Work with the post-silicon team on debug support and to help root-cause any failures Be upto date with the industry trends and bring-in the latest to the AMD products Work with DFT Tool Vendors and drive improvements based on our requirements REQUIREMENTS: 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes. Good understanding and exposure to SoC design and architecture Very good understanding of verif and timing concepts having handled DFT timing closure Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc Comfortable with VCS/Verdi and Mentor TK. Logical in thinking and ability to gel we'll within a team Good stakeholder management Ability to quickly adapt to changes and handle pressure Good communication and leadership skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer engineering/Electrical Engineering

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10809 Date posted 04/21/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated and skilled engineer with 4 -10 years of experience in emulation solutions development. You bring a strong foundation in programming concepts using C/C++ and an understanding of digital design. Your expertise includes HDL languages such as System Verilog and Verilog, and you are familiar with protocols like AXI, AMBA, JTAG, AVB, CAN, and TSN. You thrive in collaborative environments and have excellent communication skills. Your educational background includes a B.E/ B.Tech/ M.Tech in Electronic & Communication or Computer Science Engineering. You are passionate about developing cutting-edge emulation solutions for semiconductor customers and are eager to engage in both software development and synthesizable RTL development. What You’ll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN, CHI, Ethernet, PCIe, CXL, UCIe CSI, DSI, DP, UFS, MMC, HDMI, DRAM. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You’ll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus. Who You Are: A team player with excellent communication skills. Detail-oriented and capable of working independently. Adaptable and eager to learn new technologies and methodologies. Proactive in identifying and solving problems. Passionate about delivering high-quality solutions. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing state-of-the-art emulation solutions for semiconductor customers. The team collaborates closely with other engineering groups within Synopsys to ensure seamless integration and optimal performance of our products. We value creativity, continuous learning, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10811 Date posted 04/21/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated and skilled engineer with 4-10 years of experience in emulation solutions development. You bring a strong foundation in programming concepts using C/C++ and an understanding of digital design. Your expertise includes HDL languages such as System Verilog and Verilog, and you are familiar with protocols like AXI, AMBA, JTAG, AVB, CAN, and TSN. You thrive in collaborative environments and have excellent communication skills. Your educational background includes a B.E/ B.Tech/ M.Tech in Electronic & Communication or Computer Science Engineering. You are passionate about developing cutting-edge emulation solutions for semiconductor customers and are eager to engage in both software development and synthesizable RTL development. What You’ll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN, CHI, Ethernet, PCIe, CXL, UCIe CSI, DSI, DP, UFS, MMC, HDMI, DRAM. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You’ll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus. Who You Are: A team player with excellent communication skills. Detail-oriented and capable of working independently. Adaptable and eager to learn new technologies and methodologies. Proactive in identifying and solving problems. Passionate about delivering high-quality solutions. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing state-of-the-art emulation solutions for semiconductor customers. The team collaborates closely with other engineering groups within Synopsys to ensure seamless integration and optimal performance of our products. We value creativity, continuous learning, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

General Information Req # WD00079021 Career area: Manufacturing Country/Region: India State: Puducherry (Pondicherry) City: Pondicherry Date: Monday, March 3, 2025 Working time: Full-time Additional Locations : India - Puducherry (Pondicherry) - Pondicherry Why Work at Lenovo We are Lenovo. We do what we say. We own what we do. We WOW our customers. Lenovo is a US$57 billion revenue global technology powerhouse, ranked #248 in the Fortune Global 500, and serving millions of customers every day in 180 markets. Focused on a bold vision to deliver Smarter Technology for All, Lenovo has built on its success as the world’s largest PC company with a full-stack portfolio of AI-enabled, AI-ready, and AI-optimized devices (PCs, workstations, smartphones, tablets), infrastructure (server, storage, edge, high performance computing and software defined infrastructure), software, solutions, and services. Lenovo’s continued investment in world-changing innovation is building a more equitable, trustworthy, and smarter future for everyone, everywhere. Lenovo is listed on the Hong Kong stock exchange under Lenovo Group Limited (HKSE: 992) (ADR: LNVGY). This transformation together with Lenovo’s world-changing innovation is building a more inclusive, trustworthy, and smarter future for everyone, everywhere. To find out more visit www.lenovo.com, and read about the latest news via our StoryHub. Description and Requirements Perform real-time debugging and troubleshooting of server hardware, including motherboards, processors, memory, storage devices, power supplies, and networking components. Analyze and diagnose failures using diagnostic Tools, Jigs, Test codes, and other debugging equipment. Investigate manufacturing defects, determine root causes, and implement corrective actions to improve product quality and reliability. Work closely with Production, Quality, and Engineering teams to resolve issues and drive continuous improvement in server manufacturing processes. Develop and document debugging procedures, failure analysis reports, and corrective action plans. Support the implementation of process improvements, test automation, and predictive maintenance techniques to reduce failure rates. Collaborate with suppliers Quality team and Production team to resolve component-related issues and improve serviceability. Maintain compliance with industry standards, safety regulations, and company quality policies. Train and mentor production technicians on debugging best practices and failure analysis techniques. Required Qualifications: Bachelor’s degree/Diploma in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. 5+ years of experience in production debugging, hardware failure analysis, or server manufacturing. Strong knowledge of server architecture, including CPUs, memory, storage, PCIe, and power distribution. Proficiency in using debugging tools such as oscilloscopes, logic analyzers, JTAG debuggers, and thermal imaging cameras. Experience with BIOS, firmware, and system-level debugging. Familiarity with automated testing tools, diagnostic software, and scripting languages (Python, Bash, etc.) is a plus. Hands-on experience with industry-standard failure analysis methodologies such as FMEA, root cause analysis, and 8D problem-solving. Excellent analytical, troubleshooting, and problem-solving skills. Strong communication and collaboration skills to work effectively with cross-functional teams. Ability to work in a fast-paced, high-volume manufacturing environment with minimal supervision. Additional Locations : India - Puducherry (Pondicherry) - Pondicherry India * India - Puducherry , * India - Puducherry (Pondicherry) India - Puducherry (Pondicherry) - Pondicherry NOTICE FOR PUBLIC At Lenovo, we follow strict policies and legal compliance for our recruitment process, which includes role alignment, employment terms discussion, final selection and offer approval, and recording transactions in our internal system. Interviews may be conducted via audio, video, or in-person depending on the role, and you will always meet with an official Lenovo representative. Please beware of fraudulent recruiters posing as Lenovo representatives. They may request cash deposits or personal information. Always apply through official Lenovo channels and never share sensitive information. Lenovo does not solicit money or sensitive information from applicants and will not request payments for training or equipment. Kindly verify job offers through the official Lenovo careers page or contact IndiaTA@lenovo.com. Stay informed and cautious to protect yourself from recruitment fraud. Report any suspicious activity to local authorities.