333 Ips Jobs - Page 6

"> Search Jobs Find Jobs For Where Search Jobs SOC Engineering, Staff Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 8601 Remote Eligible No Date Posted 22/04/2025 Alternate Job Titles: Staff SOC Engineer Senior SOC Design Engineer Lead SOC Engineer We Are: You Are: You are an experienced and motivated SOC Engineer with a passion for cutting-edge technology and innovation. With a strong background in system-on-chip (SOC) design and verification, you bring a wealth of knowledge and a keen eye for detail. You thrive in a collaborative environment, working seamlessly with cross-functional teams to deliver high-quality solutions. Your problem-solving skills are exceptional, and you have a proven track record of successfully managing complex projects. You are proactive, adaptable, and always eager to learn and grow in a dynamic and fast-paced setting. What You ll Be Doing: Designing and implementing SOC solutions for various applications, ensuring high performance and reliability. Collaborating with cross-functional teams to define and develop SOC architecture and specifications. Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements. Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives. Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies. Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation. Job Description and Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors. Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC. Understand the design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure that the design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer. Required B.E/B. Tech/M.E/M. Tech in electronics with 4-9 years experience in RTL Design and Verification. Hands-on experience on static verification tools such as Spyglass performing LINT, CDC, RDC. Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossing. Good conceptual understanding of RTL rule checks. Hands-on experience on synthesis and timing constraints development. Candidates with experience on ARM based technologies (Coresight Debug, Processor architecture, etc.) will be preferred. The Team You ll Be A Part Of: You will join a highly skilled and motivated team dedicated to developing advanced SOC solutions. Our team focuses on innovation, collaboration, and excellence, working together to deliver high-quality designs that drive technological advancements. We value diversity and inclusion, fostering a supportive and dynamic environment where every team member can thrive and contribute to our success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

We are seeking innovative and out-of-the-box thinking Design For Test (DFT) Engineers to be a part of the Fast Solution Team under the Test Group at Synopsys. You are someone who thrives in a project-oriented environment, delivering comprehensive DFT solutions ranging from integration to silicon bring-up for customers designing digital ICs of varying complexity. You excel in assessing customer methodologies and flows, gathering requirements, and proposing solutions. You are adept at providing technical support to ensure customer success and satisfaction, winning new customers through product demonstrations, evaluations, and competitive benchmarking. You are skilled in resolving technical problems, training, and account management, and you can interact effectively with end-users at customer sites and with first-level managers. You are also responsible for working with Solution Architects to develop and productize the next-gen test technologies. Your role involves prototyping new methodologies, analyzing gathered data, identifying the viability of technology, and presenting the findings under the guidance of a Solution Architect. What You ll Be Doing: Providing expertise for test solutions during design planning, budgeting, and implementation. MBIST implementation and validation, including BIST architecture planning, memory grouping, pattern generation, validation, silicon bring-up, diagnostics analysis, and debug. Participating in customer s design and flow reviews. Driving, prototyping, and developing new Design for Test methodologies. Multitasking across various issues and priorities to help customers exploit new technologies. Collaborating with Solution Architects to develop and productize next-gen test technologies. The Impact You Will Have: Enhancing Synopsys ability to deliver cutting-edge test solutions that meet customer needs. Contributing to the successful integration and silicon bring-up of complex digital ICs. Ensuring high customer satisfaction through effective technical support and problem resolution. Driving innovation in test methodologies and technologies. Supporting the development of next-gen test technologies that push the boundaries of whats possible. Playing a key role in winning new customers and expanding Synopsys market presence. What You ll Need: Minimum BS+10 years of relevant experience/MS+8 years of relevant experience in Electrical Engineering, Computer Engineering, or other relevant fields of study. Experience with RTL coding, DFT insertion, ATPG, MBIST architecture planning, insertion, validation, pattern generation, and silicon bring-up. Excellent knowledge of memory BIST flows, memory fault models, MBIST algorithms, hard/soft repair, and eFuse repair flow. Experience in handling memory BIST for large, complex SoCs with various IPs. Exposure to MBIST of automotive designs is a plus. Good understanding of protocols like 1149.1, 1500, 1687.

Working on producing highly optimized hardware IP for the ARC family of configurable processors. Collaborating with an international multi-disciplinary team on the qualification, benchmarking, and test chip implementation of new microprocessor IPs. Participating in in-house test chip designs and development platforms to learn about potential applications of our microprocessor IPs. Assisting in customer sales and design-ins of our IP, providing technical support and expertise. Implementing a comprehensive implementation flow that is configurable and supported by Synopsys memory compilers and standard cell libraries. Ensuring the highest standards of quality in physical verification and IR processes. The Impact You Will Have: Contributing to the development of cutting-edge microprocessor IPs that set industry standards. Enhancing the capabilities of our customers by enabling them to develop highly sophisticated embedded designs. Driving the success of our products through your expertise in physical verification and IR. Supporting our sales team by providing technical insights and facilitating design-ins. Improving the efficiency and configurability of our implementation flows. Helping to position Synopsys as a leader in the semiconductor industry through continuous innovation. What You ll Need: Bachelor s degree in electronics engineering or computer science; Master s degree is a plus. Minimum of 5 years of related experience in physical verification and IR. Proficiency in Verilog/VHDL. Expertise in Unix, Perl, and TCL scripting. Understanding of microprocessor design is highly desirable. Who You Are: A detail-oriented professional with strong analytical skills. An excellent communicator with the ability to convey complex technical concepts effectively. A team player who thrives in a collaborative, international environment. A proactive learner who stays updated with the latest industry trends and technologies. A problem solver who enjoys tackling challenging technical issues

The candidate would be part of the VIP group responsible for development of Verification IPs. Core responsibilities would include Designing and developing the VIP/Test-bench, Creating Verification plans, Coding sequences/Test-scenarios, Coverage driven verification. The responsibility would also include enhancement of the existing Verification IP products and interface with customers during VIP deployment. This is an opportunity to work with best-in-class verification, debug tools, Design IP & close collaboration with best protocol experts in the industry. You will work with highly professional and motivated colleagues who value and support your contribution. Requirements: Bachelors/masters with good academic record. 7+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a strong work exposure on any of the industry standard protocols like PCIe, USB, Ethernet, MIPI etc.. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure.

Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above ~2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. Enhancing the reliability and integration of mixed signal macro IPs. Contributing to the overall success and innovation of Synopsys IP solutions. Mentoring junior engineers, fostering a culture of continuous learning and improvement. Representing Synopsys in key projects, influencing the direction and success of our initiatives. What You ll Need: Minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in tools like DC, ICC2, StarRC, and PT-SI. Strong understanding of timing closure, power signoff, and mixed signal macro IP integration. Experience with DDR power signoff and clock tree building. Excellent problem-solving and analytical skills. Who You Are: A strong team player with excellent communication skills. Independent and collaborative, capable of working with minimal supervision. Creative and innovative, able to develop unique solutions to complex problems. Detail-oriented and organized, ensuring high-quality project outcomes. Passionate about continuous learning and professional growth.

We are looking for a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities. Responsibilities include complete digital implementation from RTL to GDS including Synthesis, Floor-Planning, Power Planning and Analysis, CTS, Placement and Routing, STA, Formal Verification, EMIR Signoff and physical verification. The individual will contribute both on the implementation side as well as flow development for a variety of advanced high performance interface IPs, Test chips & Subsystems at latest techno nodes. The successful candidate: - has solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design. - has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints - has good scripting & programming skills (Perl, Tcl, Python etc); knowledge of CAD automation methods. - Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements - Independent, timely decision maker and able to cope with interrupts - Knowledge of IP Subsystem implementation & FE flows are added advantages 8+ years of hands-on experience in ASIC physical implementation and EDA tools with recent contribution to project tape-outs. Must demonstrate knowledge of the Synopsys tools, flows and methodologies including Design Compiler, IC Compiler/2, Fusion Compiler, Primetime, Formality, Star-RCXT, Hercules/ICV and other industry tools.

Driving the physical implementation of high-speed interface IPs and test-chips from RTL to GDS. Managing timing and physical sign-off to ensure successful project tape-outs. Collaborating with multiple functional groups, including front-end, analog, and CAD teams. Focusing on advanced SerDes developments, including the latest 56/112G PAM4 standards. Leading the physical design team to ensure on-time delivery of projects. Utilizing your software and scripting skills to enhance CAD automation methods. The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything. Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements. Reducing the risk and time-to-market for differentiated products. Driving technological innovation through advanced SerDes development. Enhancing Synopsys reputation as a leader in chip design and verification. Supporting the companys mission to power the world s most advanced technologies for chip design and software security. What You ll Need: 8+ years of physical design experience with recent contributions to project tape-outs. Intimate understanding of the full design cycle from RTL to GDSII, including chip level. Experience with advanced FinFET nodes, TSMC 16 nanometer or below. Solid understanding of IC design, implementation flows, and methodologies for deep submicron design. Proven track record for technical steering of physical design teams for on-time delivery. Who You Are: Excellent communicator with the ability to engage with peer groups and customers. Autonomous and capable of making timely judgments. Proficient in software and scripting skills (Perl, Tcl, Python). Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs. Able to travel internationally as required.

Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs. Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability. Utilizing advanced tools and methodologies to mitigate deep submicron effects. Conducting floor-planning, routing, and top-level verification. Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations. Optimizing power routes and addressing EM and IR considerations for robust designs. The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components. Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments. Ensuring seamless integration and functionality of our IPs in diverse applications. Improving design efficiency and manufacturability through advanced layout techniques. Contributing to the success of our product development lifecycle by delivering high-quality designs. Supporting our mission to lead in chip design and IP integration, shaping the future of technology. What You ll Need: 6+ years of experience in Analog Mixed-Signal layout and verification. Advanced understanding of deep submicron effects and mitigation techniques. Proficiency in using advanced layout design tools and methodologies. Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below. Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE.

Developing next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) Executing projects in advanced technologies with a focus on analytical and problem-solving skills Designing high-speed IOs for memory interface PHY IP in CMOS/FinFET/GAA Collaborating with cross-functional teams globally to achieve project goals Ensuring product quality and efficiency in all design tasks Staying updated with the latest industry standards and technological advancements The Impact You Will Have: Driving the development of innovative high-speed memory interface PHY IPs Contributing to the integration of advanced capabilities in SoCs Enhancing the performance, power efficiency, and size optimization of target applications Reducing risk and accelerating time-to-market for differentiated products Collaborating with global teams to deliver high-quality products Setting industry benchmarks for advanced analog design technologies What You ll Need: BTech/MTech degree in a relevant field 3+ years of experience in analog design fundamentals and device physics Proficiency in high-speed IO designs in advanced technologies Experience with ESD and reliability concepts Knowledge of JEDEC requirements for memory interfaces and standards Familiarity with signal integrity and/or power integrity is a plus Who You Are: An analytical thinker with strong problem-solving skills A collaborative team player with excellent communication and interpersonal skills Detail-oriented and capable of executing tasks with high precision and efficiency Adaptable and eager to learn new technologies and industry standards Passionate about innovation and technological advancement

We are seeking an experienced analog design manager to lead our high-performance SERDES IP design team. This senior role will oversee all aspects of analog IP development and execution for cutting-edge SerDes architectures targeting advanced process nodes. Responsibilities: - Manage and mentor a team of 8-10 senior analog designers focused on high-speed SerDes IP development across multiple projects - Define architecture specifications and circuit implementation requirements for next-generation SerDes PHY IPs - Ensure adherence to project schedules, quality metrics, power/area targets through effective team oversight - Collaborate with cross-functional teams (digital design, physical design, CAD) to integrate analog IP components - Partner with process engineering teams to enable robust analog IP across advanced FinFET nodes - Continuously drive design methodology improvements and adoption of latest EDA tools/flows - Develop and manage operational plan, including staffing, budgets and resource allocation - Hire, develop and retain top analog engineering talent through active mentorship Requirements: - Bachelors degree in electrical engineering; advanced degree preferred -8+ years of experience in analog/mixed-signal IC design with a strong background in SerDes architectures - 2+ years of people management experience leading high-performance analog design teams - Proven expertise in high-speed I/O design, architectures, circuits, and layout implementation - Extensive knowledge of CDR, DFE, CTLE, EQ, decision feedback equalizer design techniques - Hands-on experience with analog/mixed-signal design flows, tools (Cadence, Synopsys), modeling - Understanding of FinFET transistor characteristics and design challenges at advanced nodes - Strong project management skills with the ability to manage multiple priorities - Excellent communication and people leadership abilities to motivate cross-functional teams

Leading the development of next-generation high-speed memory interface IPs (DDR/HBM/UCIe). Driving projects in new technologies with a focus on analytical and problem-solving skills. Acting as a technical mentor to ensure schedules and product quality are met. Developing and maintaining project schedules, working in cross-functional settings. Demonstrating proficiency in design concepts and methodologies. Taking on people management responsibilities, guiding and developing your team. The Impact You Will Have: Contributing to the development of cutting-edge memory interface PHY IPs that drive technological advancements. Ensuring high-quality product development through effective leadership and technical expertise. Mentoring and guiding your team to achieve their full potential and meet project goals. Collaborating with cross-functional teams to drive innovation and efficiency. Maintaining Synopsys leadership position in the semiconductor industry by delivering top-notch IPs. Shaping the future of technology through continuous innovation and excellence. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or related field. 10+ years of experience in analog/mixed signal design. Knowledge of deep submicron process technologies - CMOS/FinFET/GAA. In-depth understanding of JEDEC requirements for memory interfaces and standards. Familiarity with ESD concepts and signal integrity/power integrity is a plus. Proven ability to lead projects and deliver high-quality products efficiently. Excellent written and verbal communication skills. Who You Are: A visionary leader with a passion for analog design and innovation. Analytical and detail-oriented with strong problem-solving skills. An effective communicator and mentor, capable of guiding and developing your team. Proactive and adaptable, able to thrive in cross-functional settings. Committed to delivering high-quality products and driving technological advancements.

Leading the development of next-generation DDR/HBM/UCIe IPs. Advising team members to meet schedules and resolve problems effectively. Taking on project leadership roles and contributing to complex project aspects. Developing and maintaining project schedules, ensuring timely delivery. Collaborating in cross-functional settings to drive project success. Demonstrating proficiency in design and verification processes. The Impact You Will Have: Driving innovation in next-generation DDR/HBM/UCIe IP development. Enhancing the performance and capabilities of our Silicon IP portfolio. Ensuring high-quality and efficient project execution. Mentoring and guiding team members to achieve their full potential. Contributing to the rapid integration of advanced technologies into SoCs. Helping Synopsys maintain its leadership in the semiconductor industry. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or a related field. 8+ years of experience in CMOS circuit design and layout methodology. In-depth understanding of analog/mixed-signal circuitry and ESD concepts. Familiarity with analog mixed-signal simulation strategies. Knowledge of JEDEC standards for DDR interfaces and ASIC design flow. Who You Are: Visionary leader with strong problem-solving skills. Excellent communicator with the ability to lead and mentor teams. Detail-oriented and proficient in project management. Adaptable and able to thrive in cross-functional settings. Committed to achieving high standards of product quality and efficiency

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * You will be involved in creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chi-to-chip, die-to-die, coherent and non-coherent design topologies. * You will be responsible for functional verification involving coherent and non-coherent IP designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification.

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * You will be responsible for functional verification involving coherent and non-coherent IP designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Principal Responsibility: Develop CMM programs for NPI parts in accordance with AS9100 & ASME Y14.5 standards Ensure timely completion of CMM programming as per project timelines Conduct prove-outs of CMM programs on the shop floor Create CMM programs for CI parts Address day-to-day quality issues on the shop floor in a timely manner Review drawings and specifications to define appropriate inspection criteria, following best practices Perform MSA (Measurement System Analysis) for validated CMM programs and review IPS for NPI parts Demonstrate strong understanding of GRR for all types of manual measuring instruments Prepare and review inspection planning sheets Possess basic knowledge of FAIR & PPAP documentation as per aerospace industry standards Proficiency in CMM programming using MCOSMOS v4.5 and above

Location: Delhi (with travel) Experience: 4-5+ Years Reporting To: Editor-in-Chief Role Summary We are seeking a Features Editor with a strong editorial vision, storytelling expertise, and a deep passion for travel and luxury. This role is ideal for someone who thrives on curating compelling narratives, securing exclusive interviews, and shaping the voice of Travel + Leisure India South Asia across print and digital platforms. The ideal candidate will have a strong network in the media, lifestyle, and luxury industries and will play a key role in shaping the magazine s features, special issues, and long-form storytelling. Key Responsibilities 1. Editorial Vision Content Development Curate and commission features that align with Travel + Leisure s editorial direction, ensuring a mix of destination coverage, culture, luxury, and experiential travel, both profiles, industry features, and opinion articles. Develop deep-dive, narrative-driven pieces across print, digital, and video formats. Lead special editorial projects, including special supplements, themed issues, anniversary editions, and multi-platform storytelling campaigns. 2. Industry Engagement Story Sourcing Maintain and grow relationships with writers, photographers, content creators, and thought leaders in travel, hospitality, and luxury. Secure exclusive interviews with global travel icons, hoteliers, designers, and cultural influencers. Identify emerging travel trends, ensuring the brand remains ahead of the curve. 3. Cross-Platform Integration Brand Growth Work closely with digital and social teams to ensure that print features translate seamlessly to digital and social media. Support editorial IPs, such as roundtables, video series, and podcasts, expanding the brand s storytelling footprint. Oversee native content and branded features, ensuring they maintain editorial integrity while meeting client objectives. 4. Live Events Special Initiatives Collaborate on high-profile industry events, including the Delicious Dining Awards, Indias Best Awards, roundtables, and luxury brand partnerships. Represent Travel + Leisure India South Asia at global travel conferences, fashion weeks, and hospitality summits. Drive editorial curation for live panels, interviews, and special projects that elevate the brand s thought leadership. 5. Editorial Calendar Performance Tracking Ensure the editorial calendar is aligned across print, digital, and social platforms, reflecting seasonal, industry, and cultural moments. Collaborate with data and insights teams to track reader engagement, using analytics to refine editorial strategies. Key Skills Competencies Editorial Content Expertise Strong experience in writing, editing, and commissioning long-form travel and luxury features. A deep understanding of narrative journalism, luxury media, and experiential storytelling. Network Industry Knowledge Established relationships with writers, photographers, PR teams, and cultural tastemakers. Knowledge of global travel trends, hospitality, FB, fashion, and luxury lifestyle. Strategic Cross-Platform Thinking Ability to craft multi-platform content strategies that extend across print, digital, video, and events. Experience with SEO, CMS platforms, and audience engagement strategies. Qualifications Experience Bachelor s or Master s degree in journalism, communications, or related fields. 4-5+ years of experience in editorial roles within luxury, lifestyle, or travel media. A proven ability to deliver impactful, high-quality editorial content. What We Offer A dynamic and fast-paced work environment at the intersection of travel, luxury, and media. Opportunities to work with leading global brands, industry pioneers, and creative visionaries. Competitive salary, travel opportunities, and a platform to shape premium travel journalism in India South Asia. About Us BurdaLuxury is one of Asia s most vibrant and progressive independent media houses. Our portfolio includes a variety of successful regional publishing brands in lifestyle and luxury markets across Hong Kong, India, Malaysia, Singapore, and Thailand. Print publications include AUGUSTMAN, HELLO! Magazine Thailand, Prestige, and PIN Prestige. Digital offerings include Lifestyleasia.com, Augustman.com, PrestigeOnline.com and PinPrestige.com. BurdaLuxury is part of the Hubert Burda Media family, one of the largest media companies in Germany. Burda is active in 17 countries, employs more than 12,000 people and publishes around 600 products. If you re passionate about redefining the future of travel media, we d love to hear from you.

Role Summary We are seeking a Features Editor with a strong editorial vision, storytelling expertise, and a deep passion for travel and luxury. This role is ideal for someone who thrives on curating compelling narratives, securing exclusive interviews, and shaping the voice of Travel + Leisure India South Asia across print and digital platforms. The ideal candidate will have a strong network in the media, lifestyle, and luxury industries and will play a key role in shaping the magazine s features, special issues, and long-form storytelling. Key Responsibilities 1. Editorial Vision Content Development Curate and commission features that align with Travel + Leisure s editorial direction, ensuring a mix of destination coverage, culture, luxury, and experiential travel, both profiles, industry features, and opinion articles. Develop deep-dive, narrative-driven pieces across print, digital, and video formats. Lead special editorial projects, including special supplements, themed issues, anniversary editions, and multi-platform storytelling campaigns. 2. Industry Engagement Story Sourcing Maintain and grow relationships with writers, photographers, content creators, and thought leaders in travel, hospitality, and luxury. Secure exclusive interviews with global travel icons, hoteliers, designers, and cultural influencers. Identify emerging travel trends, ensuring the brand remains ahead of the curve. 3. Cross-Platform Integration Brand Growth Work closely with digital and social teams to ensure that print features translate seamlessly to digital and social media. Support editorial IPs, such as roundtables, video series, and podcasts, expanding the brand s storytelling footprint. Oversee native content and branded features, ensuring they maintain editorial integrity while meeting client objectives. 4. Live Events Special Initiatives Collaborate on high-profile industry events, including the Delicious Dining Awards, Indias Best Awards, roundtables, and luxury brand partnerships. Represent Travel + Leisure India South Asia at global travel conferences, fashion weeks, and hospitality summits. Drive editorial curation for live panels, interviews, and special projects that elevate the brand s thought leadership. 5. Editorial Calendar Performance Tracking Ensure the editorial calendar is aligned across print, digital, and social platforms, reflecting seasonal, industry, and cultural moments. Collaborate with data and insights teams to track reader engagement, using analytics to refine editorial strategies. Key Skills Competencies Editorial Content Expertise Strong experience in writing, editing, and commissioning long-form travel and luxury features. A deep understanding of narrative journalism, luxury media, and experiential storytelling. Network Industry Knowledge Established relationships with writers, photographers, PR teams, and cultural tastemakers. Knowledge of global travel trends, hospitality, FB, fashion, and luxury lifestyle. Strategic Cross-Platform Thinking Ability to craft multi-platform content strategies that extend across print, digital, video, and events. Experience with SEO, CMS platforms, and audience engagement strategies. Qualifications Experience Bachelor s or Master s degree in journalism, communications, or related fields. 4-5+ years of experience in editorial roles within luxury, lifestyle, or travel media. A proven ability to deliver impactful, high-quality editorial content. What We Offer A dynamic and fast-paced work environment at the intersection of travel, luxury, and media. Opportunities to work with leading global brands, industry pioneers, and creative visionaries. Competitive salary, travel opportunities, and a platform to shape premium travel journalism in India South Asia.

This role includes defining and developing practice offerings, driving pre-sales and delivery support, showcasing thought leadership, and fostering team growth through competency development. Essential skills include expertise in AI/ML, Data Science, BI, and Data Engineering, along with leadership and pre-sales experience. Why Choose Ideas2IT: Ideas2IT has all the good attributes of a product startup and a services company. Since we launch our products, you will have ample opportunities to learn and contribute. However, single-product companies stagnate in the technologies they use. In our multiple product initiatives and customer-facing projects, you can work on various technologies. AGI is going to change the world. Big companies like Microsoft are betting heavily on this (see here and here ). We are following suit. As a Technical Architect, exclusively focus on engineering complex products. What s in it for you You will define, develop, and maintain the AI, Data, and Analytics practice offerings portfolio. Opportunity to work on pre-sales activities, including proposals, estimations, PoCs, presentations, and demos. Lead project execution, deploying team members, and overseeing projects to ensure high-quality delivery. Engage in thought leadership by contributing to blogs, whitepapers, and social media. Drive people leadership by hiring, mentoring, and upskilling team members through structured programs. Here s what you ll bring Prior experience in a Practice Manager / Practice Head role in relevant areas (AI, Data Analytics): 8-10 years. Overall (tech) industry experience: 15-20 years. Expertise in AI, Data, Analytics, BI, DWH, ML, and related technologies. Strong leadership skills with the ability to mentor, coach, and motivate team members. Pre-sales and practice management expertise. Customer interfacing, presentation, and consulting skills. Technology expertise in Cloud, Web, and Mobile Applications, and Automation. Consulting and sales experience with domain knowledge in verticals like Healthcare or BFSI. Experience in developing thought leadership collateral such as IPs, solutions, and frameworks. Ability to design competency development and certification programs for team members. Proven track record of scaling practices and achieving high revenue growth. Graduate / Post Graduate Degree Any qualifications (e.g., certifications) in leadership/people management will be a plus.

Position Summary Role and Responsibilities About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Roles and Responsibilities Windows Driver development Design, Development and support windows driver development for PCI/PCIe/PXI/PXIe interfaces to communicate with embedded platforms Work with Architecture, HW and other stakeholders to understand requirements and product architecture Develop unit test frameworks Integrate and cover Windows certification for device drivers Required qualifications Electronics, Electrical or Computer science graduate with 6-10 years of experience Experience in designing, coding and debugging in Windows, C/C++/C# Kernel or device driver experience with understanding of HW/SW interaction Experience in System SW development on Windows Experience with developing software communicating to embedded platforms At least 2 years of experience with drivers on PCIe Experience - 6 to 10 Years Qualifications B.Tech/B.E/M.Tech/M.E Disclaimer Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law. Skills and Qualifications * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here .

Position Summary SRAM design group in bangalore developes various types of SRAMs , Registerfiles and ROMis in advanced technology nodes like 4nm, 2nm and beyond. The team is responsible for delivering highly competitive memories for the SAMSUNG Foundry customers. Provides an unique opportunity to the individuals, who are willing innovate and solve the most challenging problem in the field of circuit design. Samsung Foundry being a pioneer in new device technology, it creates ample opportunities to the circuit designer to innovate and design highly competitive IPs. Role and Responsibilities Design highly competetive circuits to meet peroformance/power specificiations requested by customers Guide and lead a group of engineers to deliver the SRAM IP in the given timelines Analyse circuits and indentify potential robustness gaps and find solutions to improve robustness of the design. Own the responsibility from SPEC to GDS and DK delivery. Review circuits, robustness reports and identify potential robustness issues. Review Layouts and suggest improvement areas to achieve competitive PPA Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC Must be able to communicate effectively across different teams. Skills and Qualifications Master/Bachelor in electronics Working experience (10+years) in preferably Memory design Understanding of RC network and finfet fundamentals are necessary. Custom or Compiler SRAM/ROM development experience Fundamentals of process variability and its effect on memory design Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM) Stong understanding of circuit design fundamentals Critical path modeling concept, various type of models ( RC, C, Pai, ladder) Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitics etc Analysing layout and understanding of LLE effects. Bachelors /Master degree in Computer Science, Electrical/Electronics Engineering, Engineering and 10+ years of experience in circuit design.

Experience From 2 Years - 0 Months Experience To 3 Years - 0 Months Key Requirement for the Position Good communication and negotiation skill, Customer handling Experience, Motor technical and Insurance Knowledge. Job Description To Process the claims survey done By IPS, Communication with insureds , IPS claims review, Handle salvage loss claims, Venue Contact Qualification-Diploam Or Degree in Automobilee / Mechanical Engineering .

We are seeking a highly skilled SOC Level 2 Analyst to join our global Cyber Operations team. This role is essential for maintaining our organization s security posture through continuous monitoring, detection, and response. The SOC Analyst II will operate on a rotating 24x7 shift schedule, including night shifts. Ideal candidates will have a strong background in SOC operations, incident response, and expertise in various cybersecurity tools and technologies. What you will be doing: Threat Detection and Incident Response: Monitor, analyze, and respond to global security alerts using SIEM/SOAR tools. Triage with sandboxing technologies Analyze with threat intelligence tools Investigate and respond to security events, implementing containment and recovery strategies. Expedite with AI/ML workflows and capabilities Utilize KQL for querying and correlating data to identify and address threats. Develop and manage automated detection rules and playbooks in Microsoft Sentinel. Employ Microsoft Defender and MS Purview Data Loss Prevention (DLP) tools to enhance endpoint protection and data security. Threat Hunting and Data Forensics: Conduct proactive threat hunting and data forensics to uncover potential threats. Utilize advanced threat intelligence platforms to inform and refine threat detection strategies. Develop and execute SOC playbooks to improve response and operational efficiency. Team Collaboration and Leadership: Triage and assist on complex incidents and investigations. Collaborate with USA Security escalation teams and departments to enhance overall security posture. Assist in developing and refining SOC procedures and best practices. Career Development: Opportunities for progression to SOC Lead and Architect roles. Access to continuous learning, certifications, and professional development resources. Regular performance reviews to discuss career growth and advancement. What we are looking for : Qualifications: Preferred Bachelor s degree in Computer Science, Cybersecurity, or a related field. 3-5 years of experience as a SOC analyst, preferably with lead responsibilities. Strong knowledge of KQL (Kusto Query Language) for querying and analyzing security data. Hands-on experience with Microsoft Sentinel, including rule creation, playbook implementation, and workbooks. Proficiency in Microsoft Defender and MS Purview Data Loss Prevention (DLP). Certifications such as CISSP, CEH, or CompTIA Security+ are a plus. Core Technologies and Expertise Required: Microsoft Sentinel: Experience with SIEM, rule creation, playbooks, and workbooks. KQL (Kusto Query Language): Proficiency in querying and data correlation. Microsoft Defender: Expertise in endpoint protection and threat detection. MS Purview Data Loss Prevention (DLP): Experience with data protection and loss prevention strategies. Incident Response Tools: Knowledge of containment and recovery strategies. Vulnerability Management Tools: Experience in assessments, penetration tests, and threat monitoring. Threat Intelligence Platforms: Ability to leverage and analyze threat intelligence. Network Security: Working knowledge of firewalls, IDS/IPS, and network security protocols. Data Forensics: Proficient in data forensic analysis and investigation. SOC Playbooks: Proficient in creating and managing SOC playbooks. Additional Skills: Strong understanding of incident response processes and procedures. Excellent analytical and problem-solving skills. Ability to work within a well-managed team Shift Coverage: Rotational 24x7 shifts.

As the one of the design leads of the Programmable Clock & Methodologies team in India for AMDs Adaptive-Embedded Computing products, you will be responsible for driving the development of clocking solutions that meet the high standards of AMDs AECG products. This will involve leading a team of highly skilled engineers in India, as well as collaborating with the global Clock team of experts at the San Jose office, inventing and implementing original solutions, addressing challenging clock problems in some of the industry s largest and most complex SOCs. Every new Adaptive SOC brings a new set of programable Clock challenges with their latest system and functional architectures and their adoption of new semiconductor and packaging technologies. The Global Clock team works closely with functional Architecture, Programable fabric, Integration and SW teams to craft and implement new clock solutions, including new architectures, Clock IPs and development of new tools, flows & Methodology. THE PERSON: You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems. KEY RESPONSIBILITIES: Lead floor-planning, placement, routing, custom clock tree design, and optimization. Expert knowledge and hands-on experience of the entire backend and adjacent flows, including synthesis, Floor-planning P&R, clocking, timing closure, power and IO planning Perform all aspects of design flow from feasibility analysis, logic synthesis, FP, place and route, FEV, power, timing, quality checks, and design closure. Collaborate with design, Physical design, IT/infrastructure teams to ensure successful CAD flow all the way from IP design to SoC/3DIC design. Developing Programable global Clock distribution methodologies, optimizing Clock - Skew, Signal integrity and power integrity issues for AMDs next generation of programmable product families. Large Scale Block to Block Clock timing analysis, within the Die & Die to Die Clock interposer crossing. Deep analysis of timing paths to identify and debug key issues. Collaborate with functional IP teams (RTL, Ckt, physical design, Full Chip Timing, Integration) during the implementation and qualification of a growing number of programable Clock IPs. PREFERRED EXPERIENCE: You should have a deep understanding of clocking methodologies and experience in leading teams to deliver complex projects. Working knowledge of Programable clocking is a plus. Strong working knowledge in all aspects of Physical Design and Advanced Packaging (Professional Experience: 10+ years of hands-on experience in physical design and verification, with a proven track record in chip-level PNR and successful tapeouts of complex SoC designs). You should be an expert in the development of clocking solutions and have the ability to work effectively with global teams (USA & India) to ensure that on time product delivery with high quality is met. Strong Clock fundamentals (Clock switching and gating, synchronization, Clock skew balancing, Jitter, Fmax, DCD and CDC analysis). Familiarity with test, debug, yield, post-Silicon Validation & Characterization is a plus. Working experience of Package level Clock SIPI is a plus. Proficient in STA and methodologies for timing closure and have a good understanding of noise, cross-talk, Aging and OCV effects, among others.Defined timing/SDC and placement constraints for IPs. Familiar with circuit modeling, including SPICE models, and worst-case corner selection. Familiarity with Verilog and system Verilog for design. Additionally, you should be a skilled communicator, able to provide technical guidance and mentorship to junior team members to help them develop their skills and advance their careers. ACADEMIC CREDENTIALS: Bachelor or master degree in computer engineering/Electronics or Electrical Engineering with 8-12+ years of exp.

Responsibilities: Oversee the day-to-day operations of the SOC to ensure the timely detection, response, and resolution of security incidents Lead a team of security analysts and engineers, providing guidance, support, and mentorship to ensure the effectiveness and efficiency of SOC operations Develop and implement security policies, procedures, and standards to protect the organizations systems, networks, and data assets Ensure compliance with regulatory requirements and industry standards Conduct regular security assessments and audits to identify vulnerabilities, assess risks, and recommend remediation measures Monitor security controls and technologies, such as SIEM, IDS/IPS, endpoint protection, and firewalls, to detect and respond to security threats and intrusions Develop incident response plans and play a key role in coordinating and executing incident response activities during security breaches or incidents Manage and support SIEM Management, Cyber Security, Threat Vulnerability Management, Identity Access Management Collaborate with cross-functional teams, including IT, risk management, and compliance, to align security initiatives with business objectives and regulatory requirements Prepare and present security reports, metrics, and findings to senior management and stakeholders, highlighting key security risks, trends, and performance indicators Conduct regular risk assessments and vulnerability assessments Identify and evaluate security risks and recommend mitigation strategies Stay abreast of emerging threats, vulnerabilities, and security technologies, and provide strategic guidance on security best practices and industry trends Required Skills: Strong knowledge of security technologies, protocols, and best practices Experience with security tools such as SIEM, IDS/IPS, firewalls, and vulnerability management systems and EDR solutions Excellent analytical and problem-solving skills Strong communication and interpersonal skills Ability to work independently and as part of a team Attention to detail and strong analytical abilities Ability to handle sensitive and confidential information Strong organizational and project management skills Ability to stay calm under pressure and manage multiple priorities Qualifications: Bachelors degree in computer science, information security, or a related field Masters degree preferred Minimum of 6+ years of experience in information security or related field Proven experience with security incident response, risk management, and security architecture Relevant certifications such as CISSP, CISM, CEH, GIAC, or similar are highly desirable

This MDR (Monitoring, Detection & Response) Security Architect role will report to the Cyber Security Offices Security Architecture Lead. This role is pivotal in safeguarding an organizations digital assets by designing and implementing robust systems for monitoring, detecting, and responding to cyber threats. Focusing on the continuous surveillance of the IT environment, identifying potential security incidents, and orchestrating effective responses to mitigate risks. Responsible for designing and overseeing the implementation of systems and processes that monitor for, detect, and respond to cybersecurity threats. Requiring a deep understanding of threat landscapes, security technologies, and incident response strategies to ensure GSKs security posture remains robust and resilient. Key Responsibilities: This is an individual contributor role with a focus on strategic design and innovation D evelop and maintain a comprehensive strategy for security MDR that aligns with GSK s security objectives D esign and architect security monitoring solutions that integrate with existing IT and security infrastructure E valuate and select appropriate technologies and platforms for threat detection and incident response L ead the deployment and integration of security monitoring and detection tools, such as Security Information and Event Management (SIEM) systems, intrusion detection/prevention systems (IDS/IPS), and endpoint detection and response (EDR) solutions E nsure seamless integration of monitoring and detection systems with other security tools and IT infrastructure C ollaborate with IT, DevOps, and other business units to implement security controls and technologies effectively D rive innovation in MDR capabilities by exploring and adopting new technologies and methodologies W ork closely with security operations, threat intelligence, and other teams to ensure a cohesive and coordinated approach to threat detection and response C ommunicate complex security concepts and incident details to non-technical stakeholders, ensuring understanding and appropriate action Regularly report on security status, incidents, and risks to senior leadership Basic Qualifications: 6+ years of cyber security engineering and architecture experience Extensive experience in cybersecurity monitoring, detection, and incident response. I n-depth knowledge of security technologies, including SIEM, IDS/IPS, EDR, and threat intelligence platforms. Extensive knowledge of security technology including, but not limited to, encryption, authentication and authorization, security protocols, data and privacy security, AI/ML and application development Familiarity with regulatory requirements and industry standards (e.g., NIST, ISO 27001, GDPR) Strong communication and collaboration abilities, with the capacity to engage with technical and non-technical stakeholders Ability to write, develop, and maintain technical documentation, including security standards, security strategies, and implementation plans Ability to work with multiple stakeholders to promote thoughtful, practical solutions to tough security problems Benefits: Career at one of the leading global healthcare companies Company Car or Car Allowance Long-Term incentives Contract of employment Attractive reward package (annual bonus & awards for outstanding performance, recognition awards for additional achievements and engagement, holiday benefits Life insurance and pension plan Private medical package with additional preventive healthcare services for employees and their eligible Sports cards (Multisport) Possibilities of development within the role and company s structure Extensive support of work life balance (flexible working solutions, short Fridays option, health & well-being activities) Supportive community and integration events Modern office with creative rooms, fresh fruits everyday Free car and bike parking, locker rooms and showers